Specifications

Document Revision History Page 33
Using the Design Security Features in Altera FPGAsJune 2012 Altera Corporation
Document Revision History
Table 10 lists the revision history for this application note.
Table 10. Document Revision History
Date Version Changes
June 2012 2.1
■ Updated Table 1 and Table 3.
■ Updated .ekp file verification error information.
■ Updated “Hardware Requirements” section.
June 2011 2.0
■ Updated application note for the Quartus II software version 11.0 release.
■ Changed specific device names to 40- or 28-nm FPGAs.
■ Added “Security Mode Verification” and “JTAG Secure Mode for 28-nm FPGAs” sections.
■ Added Table 1
■ Updated Table 5.
■ Added Example 3, Example 4, and Example 5
■ Updated Figure 1.
■ Minor text edits.
June 2009 1.1
■ Updated “Introduction” on page 1.
■ Updated “Overview of the Design Security Feature” on page 2.
■ Updated “Security Encryption Algorithm” on page 2.
■ Updated “Non-Volatile and Volatile Key Storage” on page 3.
■ Updated (Note 3) of Table 2 on page 4.
■ Updated “Hardware and Software Requirements” on page 4.
■ Updated (Note 1) of Table 3 on page 5.
■ Updated “Steps for Implementing a Secure Configuration Flow” on page 5.
■ Updated “Step 2a: Program the Volatile Key into the Arria II GX or Stratix IV Devices” on
page 17.
■ Updated “Step 2b: Program the Non-Volatile Key into the Arria II GX or Stratix IV Devices”
on page 18.
■ Updated “Step 3: Configure the Arria II GX or Stratix IV Devices with Encrypted
Configuration Data” on page 24.
■ Added Table 3 on page 28.
■ Updated Figure 1 on page 6 and Figure 26 on page 29.
March 2009 1.0 Initial release.