Specifications

Page 28 Security Mode Verification
Using the Design Security Features in Altera FPGAs June 2012 Altera Corporation
Example 3, Example 4, and Example 5 show the .jam files to verify the FPGAs
security modes.
Non-volatile key 0 1 1 1 0 1 0 0 0
Non-volatile key with tamper protection bit 0 1 1 1 0 1 0 0 0
Table 9. Security Mode Verification for 28-nm FPGAs (Part 2 of 2)
Security Mode Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8
Example 3. JAM File for 40-nm FPGAs (Arria II GX Devices)
STATE RESET;
STATE IDLE;
'Security Mode Identification
BOOLEAN verify_reg[6];
IRSCAN 10, $013;
WAIT 100 USEC;
DRSCAN 6, $0, CAPTURE verify_reg[5..0];
Example 4. JAM File for 40-nm FPGAs (Arria II GZ and Stratix IV Devices)
STATE RESET;
STATE IDLE;
'Key Verification
BOOLEAN verify_reg[4];
IRSCAN 10, $013;
WAIT 100 USEC;
DRSCAN 4, $0, CAPTURE verify_reg[3..0];
Example 5. JAM File for 28-nm FPGAs
STATE RESET;
STATE IDLE;
'Key Verification in JAM format
BOOLEAN verify_reg[9];
IRSCAN 10, $013;
WAIT 100 USEC;
DRSCAN 9, $0, CAPTURE verify_reg[8..0];