Specifications

Security Mode Verification Page 27
Using the Design Security Features in Altera FPGAsJune 2012 Altera Corporation
Security Mode Verification
FPGAs support the KEY_VERIFY JTAG instruction that allows you to verify the existing
security mode of the device. To check if you have successfully programmed the
volatile key, use the .jam files to automate the security mode verification steps.
f For more information about the available security modes in the FPGAs, refer to the
“Security Design” section in the in the Configuration, Design Security, and Remote
System Upgrades chapter of the respective device handbook.
Table 7 lists the KEY_VERIFY JTAG instruction.
KEY_VERIFY JTAG instruction allows you to read out the information on the security
features that are enabled on the chip. This instruction scans out associated bit values.
Table 8 and Table 9 lists the security mode and the associated bit value.
Table 7. KEY_VERIFY JTAG Instruction
JTAG Instruction Instruction Code Description
KEY_VERIFY 00 0001 0011
Connects the key verification
scan register between TDI and
TDO .
Table 8. Security Mode Verification for 40-nm FPGAs
Security Mode Supported Device Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5
No key
Arria II GX 0 0 0 0 0 0
■ Arria II GZ
■ Stratix IV
0000NANA
Volatile key
Arria II GX 1 0 0 0 0 0
■ Arria II GZ
■ Stratix IV
1000NANA
Volatile key with tamper protection
Arria II GX 1 0 0 0 1 0
■ Arria II GZ
■ Stratix IV
NA NA NA NA NA NA
Non-volatile key
Arria II GX 0 1 0 1 0 0
■ Arria II GZ
■ Stratix IV
0101NANA
Non-volatile key with tamper protection bit
Arria II GX 0 1 1 1 0 0
■ Arria II GZ
■ Stratix IV
0111NANA
Table 9. Security Mode Verification for 28-nm FPGAs (Part 1 of 2)
Security Mode Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8
Nokey 000000000
Volatile key 1 0 0 0 1 1 0 0 1
Volatile key with tamper protection 1 0 0 0 1 1 1 0 1