Specifications

Page 26 Supported Configuration Schemes
Using the Design Security Features in Altera FPGAs June 2012 Altera Corporation
1 For more information the MAX II or MAX V device and flash memory configuration
method, refer to the MAX Series Configuration Controller Using Flash Memory White
Paper.
In addition, if your system contains a common flash interface (CFI) flash memory, you
can use it for the FPGA configuration as well. The MAX II and MAX V parallel flash
loader (PFL) feature provides an efficient method to program CFI flash memory
through the JTAG interface.
f For more information about PFL, refer to the Parallel Flash Loader Megafunction User
Guide.
You can use the design security feature with other configuration features, such as the
compression and remote system upgrade features. When compression is used with
the design security feature, the configuration file is first compressed and then
encrypted in the Quartus II software. During configuration, the FPGA first decrypts
and then uncompresses the configuration file.
You can either perform boundary-scan test (BST) or use the SignalTap II logic analyzer
to analyze functional data within the FPGA. However, JTAG configuration is not
possible after the key with tamper-protection bit set is programmed into the 40-nm or
28-nm FPGAs.
When using the SignalTap II logic analyzer, you must first configure the device with
an encrypted configuration file using PS, FPP, or AS configuration modes. The design
must contain at least one instance of the SignalTap II logic analyzer. After the FPGA is
configured with a SignalTap II logic analyzer instance in the design and after the
SignalTap II logic analyzer window is opened in the Quartus II software, simply scan
the chain and the SignalTap II logic analyzer is now ready to acquire data over JTAG
interface.
JTAG Download cable —
(3)
Notes to Table 6:
(1) In this mode, the host system must send a DCLK signal that is 4x the data rate.
(2) The MicroBlaster™ tool is required to execute encrypted PS configuration using a .rbf through ByteBlaster II or
ByteBlasterMV™ download cable. For more information about configuration, refer to the Configuration Center.
(3) For volatile key programming only.
Table 6. Availability of Security Configuration Schemes (Part 2 of 2)
Configuration Scheme Configuration Method Design Security