User guide

Info. Additional Information

Referenced Documents

For more information on configuration and in-system programmability (ISP), see the

following sources:

■ AN 39: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices

■ AN 95: In-System Programmability in MAX Devices

■ Configuring Cyclone FPGAs chapter in volume 1 of the Cyclone Device Handbook

■ Configuring Cyclone II Devices chapter in volume 1 of the Cyclone II Device Handbook

■ Configuring Stratix and Stratix GX Devices chapter in volume 2 of the Stratix Device

Handbook

■ In-System Programmability Guidelines for MAX II Devices chapter in volume 1 of the

MAX II Device Handbook

■ Serial Configuration Devices Data Sheet

■ Programming & Configuration chapter in the Introduction to Quartus II manual

■ The Programming module of the Quartus II online tutorial

■ Refer to the following glossary definitions in Quartus II Help:

■ “EthernetBlaster Cable” (general description)

■ “Configuration scheme” (general description)

■ “Programming files” (general description)

■ Refer to the following procedures in Quartus II Help:

■ Programming a Single Device or Multiple Devices in JTAG or Passive Serial

Mode

■ Programming a Single Device in Active Serial Programming Mode

■ Selecting the Communications Cable for the SignalTap II Logic Analyzer

■ Refer to the following introduction and overview topics in Quartus

II Help:

■ Programmer Introduction

■ Overview: Working with Chain Description Files

■ Overview: Converting Programming Files