User manual

exp1_traffic.v (2/5)

//==== reg/wire declaration ================================

//-------- output --------------------------------------

reg [6:0] HEX0;

//-------- wires ---------------------------------------

wire clk_16; // 16MHz clock signal

wire [23:0] next_clks;

reg next_state;

reg [3:0] next_countdown;

reg [6:0] next_HEX0;

//-------- flip-flops ----------------------------------

reg [23:0] clks;

reg state;

reg [3:0] countdown;

//==== combinational part ==================================

// clock signal

clksrc clksrc1 (clk, clk_16);

assign next_clks = (state==S_PAUSE)? clks: clks+24'd1;

PLL

(input: clk, 50MHz)

(output: clk_16, 16MHz)

Output should be register.

(Critical path issue)