My First FPGA for Altera DE2-115 Board 數位電路實驗 TA: 吳柏辰 Author: Trumen
Outline • • • • • • • Complete Your Verilog Design Assign The Device Add a PLL Megafunction Assign the Pins Create a Default TimeQuest SDC File Compile and Verify Your Design Configuring the Cyclone IV E FPGA 2
Complete Your Verilog Design 3
exp1_traffic.v (1/5) module exp1_traffic ( clk, rst_n, pause, HEX0 ); It is a 10 seconds countdown system.
exp1_traffic.v (2/5) //==== reg/wire declaration ================================ //-------- output -------------------------------------Output should be register.
exp1_traffic.v (3/5) // finite state machine (state) always@(*) begin case(state) S_NORMAL: begin if(pause==1) next_state = S_PAUSE; else next_state = S_NORMAL; end S_PAUSE: begin if(pause==1) next_state = S_PAUSE; else next_state = S_NORMAL; end endcase end Cover every possible branch of every if or case to avoid latches.
exp1_traffic.v (4/5) // 7-segment Displays always@(*) begin case(countdown) 7'd0: next_HEX0 = 7'b1000000; 7'd1: next_HEX0 = 7'b1111001; 7'd2: next_HEX0 = 7'b0100100; 7'd3: next_HEX0 = 7'b0110000; 7'd4: next_HEX0 = 7'b0011001; 7'd5: next_HEX0 = 7'b0010010; 7'd6: next_HEX0 = 7'b0000010; 7'd7: next_HEX0 = 7'b1111000; 7'd8: next_HEX0 = 7'b0000000; 7'd9: next_HEX0 = 7'b0010000; default: next_HEX0 = 7'b1111111; endcase end Cover every possible branch.
exp1_traffic.
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Notepad++ (3/5) Column Mode Editing 1. Alt + Mouse dragging 2.
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Assign The Device 14
Introduction to FPGA (1/3) • A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a designer after manufacturing. • An electronic device is said to be fieldprogrammable if it can be modified "in the field".
Introduction to FPGA (2/3) • FPGAs contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together". • FPGAs can be used to implement any logical function that an ASIC could perform.
Introduction to FPGA (3/3) • Xilinx and Altera are the current FPGA market leaders and long-time industry rivals.
Altera's Main FPGA Products • Stratix series FPGAs are the largest, highest bandwidth devices, with up to 1.1 million logic elements. • Cyclone series FPGAs and are the company's lowest cost, lowest power FPGAs. • Arria series FPGAs are between the two device families above.
Altera® Development Kits http://www.altera.com/products/devkits/kit-dev_platforms.jsp • Development kits include software, reference designs, cables, and programming hardware (development board).
Installed The USB-Blaster driver (1/3) • Plug in the 12-volt adapter to provide power to the board. • Use the USB cable to connect the leftmost USB connector (the one closest to the power switch) on the DE2-115 board to a USB port on a computer that runs the Quartus II software. • Turn on the power switch on the DE2-115 board.
Installed The USB-Blaster driver (2/3) • The computer will recognize the new hardware connected to its USB port. • But it will be unable to proceed if it does not have the required driver already installed. • The DE2-115 board is programmed by using Altera USB-Blaster mechanism. If the USB-Blaster driver is not already installed, the New Hardware Wizard will appear.
Installed The USB-Blaster driver (3/3) • If the New Hardware Wizard does not appear, check the website below ⇓ http://www.altera.com/download/drivers/usb-blaster/dri-usb-blaster-vista.
Setup Licensing (1/2) 1 2 23
Setup Licensing (2/2) Only for IP 140.112.*.* 1 Make sure these items appear, and now you can compile your design.
Create a New Project 1 2 3 25
1 2 same as (top-level) file name 3 26
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Add a PLL Megafunction 32
Using Quartus Add a PLL Megafunction • A PLL uses the on-board oscillator (50 MHz for DE2-115 Board) to create a constant clock frequency as the input to the counter. • To create the clock source, you will add a prebuilt library of parameterized modules (LPM) megafunction named ALTPLL.
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Uncheck all the options 1 39
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Assign the Pins 45
Assign the Pins • Before making pin assignments… 1 2 3 46
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2 1 for DE2-115 Type “M23”, then push Enter 48 Now, you are finished creating your Quartus II design!
Create a Default TimeQuest SDC File 49
Create a Default TimeQuest SDC File • Timing settings are critically important for a successful design. • For this tutorial you will create a basic Synopsys Design Constraints File (.sdc) that the Quartus II TimeQuest Timing Analyzer uses during design compilation. • For more complex designs, you will need to consider the timing requirements more carefully.
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create_clock -period 20 [get_ports clk] create_clock -period 62.
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Compile and Verify Your Design 55
Compile Your Design • After creating your design you must compile it. • Compilation converts the design into a bitstream that can be downloaded into the FPGA. • The most important output of compilation is an SRAM Object File (.sof), which you use to program the device.
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Compilation Report • Make sure there is no error.
Program the FPGA Device • After compiling and verifying your design you are ready to program the FPGA on the development board. • You download the SOF you just created into the FPGA using the USB-Blaster circuitry on the board.
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Demo Video • 10 seconds countdown system 65
Configuring the Cyclone IV E FPGA 66
Configuring the FPGA • JTAG programming In this method of programming, named after the IEEE standards Joint Test Action Group, the configuration bit stream is downloaded directly into the Cyclone IV E FPGA. The FPGA will retain this configuration as long as power is applied to the board; the configuration information will be lost when the power is turned off.
JTAG Chain (1/2) • To use JTAG interface for configuring FPGA device, the JTAG chain on DE2-115 must form a close loop that allows Quartus II programmer to detect FPGA device.
JTAG Chain (2/2) • Shorting pin1 and pin2 on JP3 can disable the JTAG signals on HSMC connector that will form a close JTAG loop chain on DE2-115 board. Thus, only the on board FPGA device (Cyclone IV E) will be detected by Quartus II programmer.
Configuring the FPGA in JTAG Mode (1/2) • This figure illustrates the JTAG configuration setup.
Configuring the FPGA in JTAG Mode (2/2) 1. Ensure that power is applied to the DE2-115 board. 2. Configure the JTAG programming circuit by setting the RUN/PROG slide switch (SW19) to the RUN position. 3. Connect the supplied USB cable to the USB Blaster port on the DE2-115 board. 4. The FPGA can now be programmed by using the Quartus II Programmer to select a configuration bit stream file with the .sof filename extension.
Configuring the EPCS64 in AS Mode (1/2) • This figure illustrates the AS configuration setup.
Configuring the EPCS64 in AS Mode (2/2) 1. 2. Ensure that power is applied to the DE2-115 board. 3. Configure the JTAG programming circuit by setting the RUN/PROG slide switch (SW19) to the PROG position. 4. The EPCS64 chip can now be programmed by using the Quartus II Programmer to select a configuration bit stream file with the .pof filename extension. 5.
Programmer Object File • Programmer Object File is a binary file (with the extension .pof) containing the data for programming a configuration device. • A Programmer Object File for a configuration device can be generated by the Convert Programming Files command (File menu).
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The End.
Reference 1. http://en.wikipedia.org/wiki/Fieldprogrammable_gate_array 2. "My First FPGA for Altera DE2-115 Board" by Terasic Technologies Inc. 3. "DE2-115 User Manual" by Terasic Technologies Inc.
