User guide

Using the System
36
DRAM_DQ[12] PIN_AA3 SDRAM Data[12]
DRAM_DQ[13] PIN_AC2 SDRAM Data[13]
DRAM_DQ[14] PIN_AC1 SDRAM Data[14]
DRAM_DQ[15] PIN_AA5 SDRAM Data[15]
DRAM_BA_0 PIN_AE2 SDRAM Bank Address[0]
DRAM_BA_1 PIN_AE3 SDRAM Bank Address[1]
DRAM_LDQM PIN_AD2 SDRAM Low-byte Data Mask
DRAM_UDQM PIN_Y5 SDRAM High-byte Data Mask
DRAM_RAS_N PIN_AB4 SDRAM Row Address Strobe
DRAM_CAS_N PIN_AB3 SDRAM Column Address Strobe
DRAM_CKE PIN_AA6 SDRAM Clock Enable
DRAM_CLK PIN_AA7 SDRAM Clock
DRAM_WE_N PIN_AD3 SDRAM Write Enable
DRAM_CS_N PIN_AC3 SDRAM Chip Select
Table 3.15 Pin Assignment for SDRAM
Signal Name FPGA Pin No. Description
SRAM_ADDR[0] PIN_AE4 SRAM Address[0]
SRAM_ADDR[1] PIN_AF4 SRAM Address[1]
SRAM_ADDR[2] PIN_AC5 SRAM Address[2]
SRAM_ADDR[3] PIN_AC6 SRAM Address[3]
SRAM_ADDR[4] PIN_AD4 SRAM Address[4]
SRAM_ADDR[5] PIN_AD5 SRAM Address[5]
SRAM_ADDR[6] PIN_AE5 SRAM Address[6]
SRAM_ADDR[7] PIN_AF5 SRAM Address[7]
SRAM_ADDR[8] PIN_AD6 SRAM Address[8]
SRAM_ADDR[9] PIN_AD7 SRAM Address[9]
SRAM_ADDR[10] PIN_V10 SRAM Address[10]
SRAM_ADDR[11] PIN_V9 SRAM Address[11]
SRAM_ADDR[12] PIN_AC7 SRAM Address[12]
SRAM_ADDR[13] PIN_W8 SRAM Address[13]
SRAM_ADDR[14] PIN_W10 SRAM Address[14]
SRAM_ADDR[15] PIN_Y10 SRAM Address[15]
SRAM_ADDR[16] PIN_AB8 SRAM Address[16]
SRAM_ADDR[17] PIN_AC8 SRAM Address[17]
SRAM_DQ[0] PIN_AD8 SRAM Data[0]
SRAM_DQ[1] PIN_AE6 SRAM Data[1]