User guide

Using the System
14
3-3 Controlling the DE2 using Terasic Link
We designed a special link from MAX 3128 to FPGA’s user IO pins to enable users
to control the FPGA from PC using our own command set. Figure 3.4 shows the
connection scheme of the Terasic Link.
 User can refer to Chapter 11 to exercise the DE2 Control Panel which uses
Terasic Link/IP to control the board.
 DE2 Control Panel shares the same link of JTAG and NIOS II IDE control
lines – user can use ONLY one of the three links at any given time.
Figure 3.4 The Terasic Link is used to allow the software in PC side to
communicate with the API IP core inside the FPGA
3-4 XSGA Output
ADV7123 from Analog Devices is used for the 10-bit D/A conversion for video
signals. The converted signals are then connected to the 15-pin D-Sub connector
for output to VGA. The XSGA circuits can support up to 1600x1200 @ 100Hz.
Please refer to XSGA timing spec to design FPGA to avoid any problems when
connecting to real devices. For detailed information on how to use the LCD module,
users can refer to the spec under C:\DE2\Datasheet\VGA DAC
 User can refer to Figure 3.5 for the basic VGA timing: