User guide

Altera DE2 Board
7
Figure 2.2. Block Diagram of DE2 Board
2-5 DE2 Block Description
CYCLONE II 2C35 FPGA
 With 35000 LEs
 FineLine BGA 672-pin package
 475 User IOs
 With 105 M4K RAM Blocks and 483Kbit SRAM
 With 35 embedded multipliers and 4 PLLs
Altera Serial Configuration device (EPCS16) and USB Blaster Circuit
 USB Blaster built in on board for programming and user API controlling
 JTAG Mode and AS Mode are supported
 Provides EPCS16 Serial Configuration device
8Mbyte SDRAM
 Single Data Rate Synchronous Dynamic RAM memory chip
 Organized as 1M x 4 x 16 bit.
 Support access through both NIOS II and Terasic high-speed Multi-port
SDRAM Controller
1Mbyte Flash Memory (upgradeable to 4Mbyte)
 Equipped with 1Mbyte NAND Flash memory
 Layout is designed to support up to 4Mbye SDRAM
 8-bit data bus
 Support access through both NIOS II and Terasic multi-port Flash
Controller
SD Card Socket
 Provides SPI mode for SD Card access
 Support access through NIOS II with Terasic SD Card Driver
Push-button Switches