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Altera DE2 Board

Development and Education Board

Getting Started Guide

DE2 Board

Document Version 1.2 OCT. 02, 2005 by Terasic

Summary of content (85 pages)

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Altera DE2 Board Development and Education Board Getting Started Guide DE2 Board Document Version 1.2 Preliminary Version OCT.
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Altera DE2 Board Page Index CHAPTER 1 ABOUT THE KIT...................................................................................................................................... 1 1-1 KIT CONTENTS ........................................................................................................................................................ 1 1-2 ASSEMBLE THE RUBBER FEET ..........................................................................................................................
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Altera DE2 Board 5-1 POWER UP THE BOARD ........................................................................................................................................ 33 5-2 THE TOP-LEVEL VERILOG MODULE IN CYCLONE II .............................................................................................. 33 5-3 COMPILING THE DESIGN .......................................................................................................................................
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About the Kit Chapter Chapter 1 1 About the Kit The DE2 Kit provides everything you need to develop many advanced digital designs using Altera Cyclone || device. The Getting Started User Guide is written in a way to enable users to walk through many reference designs in 30 minutes. This chapter provides users key information about the kit. Kit Contents 1-1 Figure 1.1 shows the photo of the DE2 package. The DE2 Kit includes: The DE2 Board. USB Cable for FPGA programming and control.
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About the Kit Figure 1.1. The DE2 Kit Package Content Assemble the Rubber Feet 1-2 Users can use the attached bag of copper stands, silicon feet cover, and screw to create suitable feet according to users’s own applications Assemble a screw, a copper stand, and a rubber (silicon) cover as shown in Figure 1.2 for each of the 6 screw holes on DE2. Assemble the plexiglass cover attached if extra protection is desired.
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About the Kit Figure 1.2 The Rubber Feet Set Getting Help 1-3 Here are some places to get help if you encounter any problem: Email to support@terasic.
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Altera DE2 Board Chapter Chapter 2 2 Altera DE2 Board This chapter will walk you through each part of your DE2 board to illustrate the features equipped. The DE2 Board 2-1 The DE2 board is designed using the same strict design and layout practices used in high-end volume production products such as high-density PC motherboards and car infotainment systems with the highest QC standard.
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Altera DE2 Board Figure 2.1. DE2 Development Board Components & Interfaces Features 2-3 DE2 board provides users many features to enable various multimedia project development. Component selection was made according to the most popular design in volume production multimedia products such as DVD, VCD, and MP3 players. The DE2 platform allows users to quickly understand all the insight tricks to design real multimedia projects for industry.
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Altera DE2 Board 18 Red User LEDs 50MHz Oscillator and 27MHz Oscillator for external clock sources 24-bit CD-Quality Audio CODEC with line-in, line-out, and microphone-in jacks VGA DAC (10-bit high-speed triple ADCs) with VGA out connector TV Decoder (NTSC/PAL) and TV in connector 10/100 Ethernet Controller with socket. USB Host/Slave Controller with USB type A and type B connectors.
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Altera DE2 Board Figure 2.2.
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Altera DE2 Board With 4 push-button switches Debounced by Schimitter trigger Normal high and Generate one active-low pulse when the switch is pushed DPDT Switches Contains 18 DPDT Switches for user inputs.
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Altera DE2 Board video devices. 10/100 Ethernet Controller Integrated MAC and PHY with a general processor interface Supports 100Base-T and 10Base-T applications. Supports full duplex operation at 10Mb/s and 100Mb/s, with auto-MDIX Fully compliant with the IEEE 802.3u Spec Supports IP/TCP/UDP checksum generation and checking Supports back pressure mode for half-duplex mode flow control USB Host/Slave Controller Complies fully with Universal Serial Bus Specification Rev. 2.
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Altera DE2 Board used for a standard IDE device. USB Blaster Circuits and Configuration Devices Built-in USB Blaster circuits on board with enhanced features to provide DE2 Control Panel API Link. Provide both JTAG and AS mode programming mode Contains a 16Mbit (EPCS16) serial configuration device Power Up the Board to See the Demo 2-6 DE2 board comes with a preloaded bitstream to demostrate some features of the board.
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Altera DE2 Board board. Your voice will be mixed with the music played from the MP3 player. Figure 2.
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Using the System Chapter Chapter 3 3 Using the System This chapter describes how to work with each of the major components on DE2 in detail. Configuring the FPGA in JTGA Mode 3-1 DE2 provides users both JTAG and AS mode to download bitstream to the FPGA. The first and recommended method is to configure FPGA via JTAG mode. Figure 3.1 describes the block diagram of the JTAG programming method. Follow the steps below to program the FPGA: Ensure the 9V power is supplied to the DE2 Board.
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Using the System Figure 3.2 Set SW19 to RUN position for JTAG programming and normal operation Configuring the FPGA in AS Mode 3-2 The bitstream can be downloaded via Active Serial Programming mode (AS mode). By default, the switch is set to the position of RUN for JTAG mode so that the SOF bistream file is downloaded directly to the FPGA chip.
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Using the System Controlling the DE2 using Terasic Link 3-3 We designed a special link from MAX 3128 to FPGA’s user IO pins to enable users to control the FPGA from PC using our own command set. Figure 3.4 shows the connection scheme of the Terasic Link. User can refer to Chapter 11 to exercise the DE2 Control Panel which uses Terasic Link/IP to control the board.
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Using the System Figure 3.5 VGA Display Horizontal timing spec Both Horizontal and Vertical timing periods can be divided into four zones: H-Sync (a), back porch (b), front porch (d), and display interval(c). Refer to Figure 3.6 for detailed VGA timing spec on the four timing zones. Refer to Table 3.1 for the pin assignment of the associated interface. VGA mode Horizontal Timing Spec Configuration Resolution(HxV) a(us) b(us) c(us) d(us) Pixel clock(Mhz) VGA(60Hz) 640x480 3.8 1.
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Using the System Signal Name FPGA Pin No.
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Using the System 24-bit Audio CODEC 3-5 WM8731 is used to implement the 24-bit Audio CODEC on DE2. This chip provides Microphone in, Line In, and Line Out connectors. The sample rate is adjustable from 8Khz to 96Khz by using the I2C bus on DE2 board. For detailed information on how to use the audio CODEC, users can refer to the spec under C:\DE2\Datasheet\Audio CODEC. Figure 3.7 shows the circuit diagram of the audio part of DE2. The pin assignment of the associated interface is shown in Table 3.2.
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Using the System Table 3.2 Pin Assignment for Audio CODEC Using the LEDs and Switches 3-6 The DE2 Board provides 4 push buttons. All of the buttons are Schmitt Trigger de-bounced. When a push button is pressed, only one zero pulse will be generated. There are also 18 toggle switches on the DE2 boards for users to set HIGH/LOW to the 18 GPIOs of the CycloneII FPGA. The DE2 Board has 9 green user LEDs and 18 red user LEDs. Figure 3.8 shows the related schematics.
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Using the System Figure 3.8 Push Buttons, Toggle Switches, and LEDs Signal Name FPGA Pin No.
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Using the System Signal Name FPGA Pin No. Description KEY[0] PIN_G26 Push Button[0] KEY[1] PIN_N23 Push Button[1] KEY[2] PIN_P23 Push Button[2] KEY[3] PIN_W26 Push Button[3] Table 3.4 Pin Assignment for Push Buttoms Signal Name FPGA Pin No.
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Using the System Using the 7-SEG Displays and LCD Module 3-7 The DE2 Board has eight 7-SEG displays and one 16x2 LCD module. The LCD module has built-in font library; users have to send control signals according to its specific timing to display desired characters at the correct location. For detailed information on how to use the LCD module, users can refer to the spec under C:\DE2\Datasheet\LCD Figure 3.9 shows the related schematics.
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Using the System Signal Name FPGA Pin No.
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Using the System HEX5[2] PIN_P7 Seven Segment Digital 5[2] HEX5[3] PIN_T9 Seven Segment Digital 5[3] HEX5[4] PIN_R5 Seven Segment Digital 5[4] HEX5[5] PIN_R4 Seven Segment Digital 5[5] HEX5[6] PIN_R3 Seven Segment Digital 5[6] HEX6[0] PIN_R2 Seven Segment Digital 6[0] HEX6[1] PIN_P4 Seven Segment Digital 6[1] HEX6[2] PIN_P3 Seven Segment Digital 6[2] HEX6[3] PIN_M2 Seven Segment Digital 6[3] HEX6[4] PIN_M3 Seven Segment Digital 6[4] HEX6[5] PIN_M5 Seven Segment Digital 6[5]
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Using the System Using the Expansion Headers 3-8 The DE2 Board provides users two 40-pin expansion headers. Each header provides DC +5V (VCC5), DC +3.3V (VCC33), two GND pins for users to build their own daughter cards using the DE2 expansion ports. Figure 3.10 shows the related schematics. The pin assignment of the associated interface is shown in Table 3.8. Figure 3.10 Two 40-pin Expansion Headers Signal Name FPGA Pin No.
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Using the System GPIO_0[8] PIN_F25 GPIO Connection 0[8] GPIO_0[9] PIN_F26 GPIO Connection 0[9] GPIO_0[10] PIN_N18 GPIO Connection 0[10] GPIO_0[11] PIN_P18 GPIO Connection 0[11] GPIO_0[12] PIN_G23 GPIO Connection 0[12] GPIO_0[13] PIN_G24 GPIO Connection 0[13] GPIO_0[14] PIN_K22 GPIO Connection 0[14] GPIO_0[15] PIN_G25 GPIO Connection 0[15] GPIO_0[16] PIN_H23 GPIO Connection 0[16] GPIO_0[17] PIN_H24 GPIO Connection 0[17] GPIO_0[18] PIN_J23 GPIO Connection 0[18] GPIO_0[19] PIN
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Using the System GPIO_1[10] PIN_N24 GPIO Connection 1[10] GPIO_1[11] PIN_P24 GPIO Connection 1[11] GPIO_1[12] PIN_R25 GPIO Connection 1[12] GPIO_1[13] PIN_R24 GPIO Connection 1[13] GPIO_1[14] PIN_R20 GPIO Connection 1[14] GPIO_1[15] PIN_T22 GPIO Connection 1[15] GPIO_1[16] PIN_T23 GPIO Connection 1[16] GPIO_1[17] PIN_T24 GPIO Connection 1[17] GPIO_1[18] PIN_T25 GPIO Connection 1[18] GPIO_1[19] PIN_T18 GPIO Connection 1[19] GPIO_1[20] PIN_T21 GPIO Connection 1[20] GPIO_1[21]
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Using the System Figure 3.11 MAX232 chip for RS-232 commnication Signal Name FPGA Pin No. Description UART_RXD PIN_C25 UART Receiver UART_TXD PIN_B25 UART Transmitter Table 3.9 Pin Assignment for Serial Ports (RS232) Using the Serial Ports(PS/2) 3-10 The DE2 Board offers standard PS/2 interface with a connector for a PS/2 keyboard or mouse. Figure 3.12 shows the schematic of the PS/2 connector and circuits. For how to use PS/2 mouse and keyboards, users can refer to http://www.
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Using the System Using the Fast Ethernet Network Controller 3-11 The DE2 board uses DM9000A for Fast Ethernet interface. The DM9000A is a fully integrated and cost-effective low pin count single chip Fast Ethernet controller with a general processor interface, a 10/100< PHY, and 4K Dword SRAM. It is designed with low power and high performance process that support 3.3V with 5V IO tolerance. Figure 3.13 shows the schematic design for the Fast Ethernet interface for DE2.
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Using the System ENET_DATA[12] PIN_B19 DM9000A DATA[12] ENET_DATA[13] PIN_A19 DM9000A DATA[13] ENET_DATA[14] PIN_E18 DM9000A DATA[14] ENET_DATA[15] PIN_D18 DM9000A DATA[15] ENET_CLK PIN_B24 DM9000A Clock 25 MHz ENET_CMD PIN_A21 DM9000A Command/Data Select, 0 = Command, 1 = Data ENET_CS_N PIN_A23 DM9000A Chip Select ENET_INT PIN_B21 DM9000A Interrupt ENET_RD_N PIN_A22 DM9000A Read ENET_WR_N PIN_B22 DM9000A Write ENET_RST_N PIN_B23 DM9000A Reset Table 3.
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Using the System Figure 3.14 TV Decoder Circuits Signal Name FPGA Pin No.
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Using the System Implementing a TV Encoder 3-13 Though the DE2 Board does not have a TV Encoder, the high-end ADV7123 (10-bit high-speed triple ADCs) can be used to implement a professional TV Encoder with the digital processing part implemented by RTL code in the FPGA. Figure 3.15 shows the block diagram of a TV Encoder implemented using the ADV7123 and the FPGA. Figure 3.14 A TV Encoder diagram implemented by 2F35 and the high-speed VGA DEC.
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Using the System Figure 3.15 USB Host and Device Circuit by ISP1362 Signal Name FPGA Pin No.
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Using the System OTG_RD_N PIN_G2 ISP1362 Read OTG_WR_N PIN_G1 ISP1362 Write OTG_RST_N PIN_G5 ISP1362 Reset OTG_INT0 PIN_B3 ISP1362 Interrupt 0 OTG_INT1 PIN_C3 ISP1362 Interrupt 1 OTG_DACK0_N PIN_C2 ISP1362 DMA Acknowledge 0 OTG_DACK1_N PIN_B2 ISP1362 DMA Acknowledge 1 OTG_DREQ0 PIN_F6 ISP1362 DMA Request 0 OTG_DREQ1 PIN_E5 ISP1362 DMA Request 1 OTG_FSPEED PIN_F3 USB Full Speed, 0 = Enable, Z = Disable OTG_LSPEED PIN_G6 USB Low Speed, 0 = Enable, Z = Disable Table 3.
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Using the System Signal Name FPGA Pin No. Description IRDA_TXD PIN_AE24 IRDA Transmitter IRDA_RXD PIN_AE25 IRDA Receiver Table 3.14 Pin Assignment for IrDA Using SDRAM/SRAM/Flash 3-16 Figure 3.16 shows the schematic of SDRAM, SRAM, and Flash Memory. The DE2 Board provides 8Mbyte SDRAM, 512KByte SRAM, and 1Mbyte Flash Memory. Figure 3.17 shows the schematic of the SDRAM/SRAM/Flash blocks. The pin assignments of the SDRAM, SRAM, and Flash are listed in Table 3.15, 3.16, and 3.17, respectively.
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Using the System Figure 3.17 SDRAM, SRAM, Flash Memory on DE2 Signal Name FPGA Pin No.
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Using the System DRAM_DQ[12] PIN_AA3 SDRAM Data[12] DRAM_DQ[13] PIN_AC2 SDRAM Data[13] DRAM_DQ[14] PIN_AC1 SDRAM Data[14] DRAM_DQ[15] PIN_AA5 SDRAM Data[15] DRAM_BA_0 PIN_AE2 SDRAM Bank Address[0] DRAM_BA_1 PIN_AE3 SDRAM Bank Address[1] DRAM_LDQM PIN_AD2 SDRAM Low-byte Data Mask DRAM_UDQM PIN_Y5 SDRAM High-byte Data Mask DRAM_RAS_N PIN_AB4 SDRAM Row Address Strobe DRAM_CAS_N PIN_AB3 SDRAM Column Address Strobe DRAM_CKE PIN_AA6 SDRAM Clock Enable DRAM_CLK PIN_AA7 SDRAM Cloc
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Using the System SRAM_DQ[2] PIN_AF6 SRAM Data[2] SRAM_DQ[3] PIN_AA9 SRAM Data[3] SRAM_DQ[4] PIN_AA10 SRAM Data[4] SRAM_DQ[5] PIN_AB10 SRAM Data[5] SRAM_DQ[6] PIN_AA11 SRAM Data[6] SRAM_DQ[7] PIN_Y11 SRAM Data[7] SRAM_DQ[8] PIN_AE7 SRAM Data[8] SRAM_DQ[9] PIN_AF7 SRAM Data[9] SRAM_DQ[10] PIN_AE8 SRAM Data[10] SRAM_DQ[11] PIN_AF8 SRAM Data[11] SRAM_DQ[12] PIN_W11 SRAM Data[12] SRAM_DQ[13] PIN_W12 SRAM Data[13] SRAM_DQ[14] PIN_AC9 SRAM Data[14] SRAM_DQ[15] PIN_AC10 SRAM
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Using the System FL_ADDR[15] PIN_AD16 FLASH Address[15] FL_ADDR[16] PIN_AE16 FLASH Address[16] FL_ADDR[17] PIN_AC15 FLASH Address[17] FL_ADDR[18] PIN_AB15 FLASH Address[18] FL_ADDR[19] PIN_AA15 FLASH Address[19] FL_DQ[0] PIN_AD19 FLASH Data[0] FL_DQ[1] PIN_AC19 FLASH Data[1] FL_DQ[2] PIN_AF20 FLASH Data[2] FL_DQ[3] PIN_AE20 FLASH Data[3] FL_DQ[4] PIN_AB20 FLASH Data[4] FL_DQ[5] PIN_AC20 FLASH Data[5] FL_DQ[6] PIN_AF21 FLASH Data[6] FL_DQ[7] PIN_AE21 FLASH Data[7] FL_CE
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Software Installation Chapter Chapter 4 4 Software Installation This chapter will walk you through each step to install the kit on your PC and bring up the board correctly. Users must ensure that all required software (QuartusII, NIOSII, Project files, and DE2 Control Panel) are installed properly so that we can proceed to the next chapters where we are doing many lab demonstrations. Install Quartus II 4-1 You need Quartus II installed on your PC to use DE2 board.
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Software Installation http://www.altera.com/support/software/drivers For Window 2000, choose Settings > Control Panel (Windows Start menu); for Window XP, choose Control Panel (Window Start Menu). Click Switch to Classic View if you are not in the classic view. Double-click the Add Hardware icon to start the Add hardware wizard and click Next to continue. Select Yes, I have already connected the hardware and then click Next.
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Software Installation control the board. Follow the steps below to install the CD-ROM Insert DE2 Lab CD-ROM into your CD-ROM drive. The menu shown in Figure 4.1 will pop up. Click on “Read Me First” and then click on “Install Software” buttons, which will install all the labs and API software into your C:\DE2. If you encounter the picture shown in Figure 4.2. Simply click on “Ignore” to continue.
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Software Installation The Top-level Verilog Module and Pin Assignment 4-5 The complete top-level pin assignment is provided in C:\DE2\DE2_TOP project Please use the pin assignment in DE2_TOP project as golden pin assignment for all your projects. The top-level Verilog file is located in C:\DE2\DE2_TOP\DE2_TOP.
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First Lab: DE2 Top-Level and Default Bitstream Chapter Chapter 5 5 First Lab: DE2 Top-Level and Default Bitstream This lab gives users the connection assignment and top-level Verilog module, which is the fundamental building block for all the other labs in this manual. The bitstream created in this Lab is used as the default bitstream loaded in DE2 board before shipping. This lab will illustrate how to compile and load the default bitstream into the DE2 Board.
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First Lab: DE2 Top-Level and Default Bitstream Figure 5.1. Menu for Opening Quartus II Project Select Quartus II project DE2_Default under C:\DE2\DE2_Default directory Please refer to Figure 5.2. Click on File Icon in the bottom of left-hand side window and select DE2_Default. Examine the file content and the IO port declaration. You will find that we provide detailed descriptions for user to understand the purpose of each pin in the top-level module.
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First Lab: DE2 Top-Level and Default Bitstream DRAM_DQ, // SDRAM Data bus 16 Bits DRAM_ADDR, // SDRAM Address bus 12 Bits DRAM_LDQM, // SDRAM Low-byte Data Mask DRAM_UDQM, // SDRAM High-byte Data Mask DRAM_WE_N, // SDRAM Write Enable DRAM_CAS_N, // SDRAM Column Addr Strobe DRAM_RAS_N, // SDRAM Row Addr Strobe DRAM_CS_N, // SDRAM Chip Select DRAM_BA_0, // SDRAM Bank Address 0 DRAM_BA_1, // SDRAM Bank Address 0 DRAM_CLK, // SDRAM Clock DRAM_CKE, // SDRAM Clock Enable //////
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First Lab: DE2 Top-Level and Default Bitstream OTG_INT1, // ISP1362 Interrupt 1 OTG_DREQ0, // ISP1362 DMA Request 0 OTG_DREQ1, // ISP1362 DMA Request 1 OTG_DACK0_N, // ISP1362 DMA Acknowledge 0 OTG_DACK1_N, // ISP1362 DMA Acknowledge 1 //////////////////// LCD Module 16X2 //////////////// LCD_ON, // LCD Power ON/OFF LCD_BLON, // LCD Back Light ON/OFF LCD_RW, // LCD Read/Write Select, // 0 = Write, 1 = Read LCD_EN, // LCD Enable LCD_RS, // LCD Command/Data Select, // 0 = Co
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First Lab: DE2 Top-Level and Default Bitstream VGA_SYNC, // VGA SYNC VGA_R, // VGA Red[9:0] VGA_G, // VGA Green[9:0] VGA_B, // VGA Blue[9:0] //////////// Ethernet Interface //////////////////////// ENET_DATA, // DM9000A DATA bus 16Bits ENET_CMD, // DM9000A Command/Data // Select, 0 = Command, 1 = Data ENET_CS_N, // DM9000A Chip Select ENET_WR_N, // DM9000A Write ENET_RD_N, // DM9000A Read ENET_RST_N, // DM9000A Reset ENET_INT, // DM9000A Interrupt ENET_CLK, // DM9000A
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First Lab: DE2 Top-Level and Default Bitstream Compiling the Design 5-3 You can click the compile button to start compilation. 1. It will create a SOF file (DE2_Default.sof) for user to program the FPGA. To program the active serial device, you need to convert programming file to POF format. Figure 5.3 shows the Convert Programming File menu. Figure 5.3. Open the menu for Converting Programming Files 2.
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First Lab: DE2 Top-Level and Default Bitstream Download Bitstream 5-4 You can click the Programmer button to perform bitstream downloading. 1. DE2 board uses USB-Blaster to download bitstream. We support both JTAG mode and Active Serial Programming mode (AS mode). By default, the switch is set to the position of RUN for JTAG mode so that the SOF bistream file is downloaded directly to the FPGA chip.
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First Lab: DE2 Top-Level and Default Bitstream Figure 5.6. Hardware Setup Menu for USB-Blaster 5. Click Close to close the Hardware Setup dialog box. 6. In the programming window, select the desired mode (JTAG or Active Serial Programming mode). 7. Click Add File button and select the desired SOF(for JTAG) or POF(for AS mode) accordingly. 8. Click Start button to download the selected bitstream. 9. In JTAG mode, you should see the behavior of the design right away.
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Lab 2: TV Box Chapter Chapter 6 Lab 2: TV Box 6 HDTV/SDTV is one of the most important multimedia technologies students and engineers should learn to meet the huge industry demand in this area. In this lab, we will implement a TV box using DE2 board. Design Descriptions 6-1 Figure 6.1 illustrates the block diagram of the entire design.
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Lab 2: TV Box VGA Timing Generator block generates standard VGA sync signals – VGA_HS and VGA_VS - to enable the display on a VGA monitor. Figure 6.1 The block diagram of the TV Box design Lab Setup and Instructions 6-2 Project Directory: C:\DE2\DE2_TV Bitstream Used: C:\DE2\DE2_TV\DE2_TV.sof or DE2_TV.pof Refer to Figure 6.2 and setup the lab according to the following steps: Connect a DVD player’s Video output to the Video IN RCA Jack of the DE2 board.
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Lab 2: TV Box Figure 6.2 The Lab Setup for TV Box Important Note for the Lab DVD Player must set to the following mode: 1. NTSC 2. 60Hz 3. 4:3 ratio 4.
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Lab 3: USB Paint Brush Chapter 7 Chapter 7 Lab 3: USB Paint Brush USB becomes the most popular communication method in many multimedia products. DE2 provides users a complete USB solution on both host and device applications. In this lab, we are implementing a Paint Brush Application with USB mouse as input device. Design Descriptions 7-1 In this lab demo, we use the device port of the Philips ISP1362 and NIOSII CPU to implement a USB mouse movement detector.
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Lab 3: USB Paint Brush Figure 7.1 The Block Diagram of the USB Paint Brush Application Lab Setup and Instructions 7-2 Project Directory: C:\DE2\UP4_NIOS_HOST_MOUSE_VGA Bitstream Used: UP4_api.sof NIOS II Workspace : C:\DE2\UP4_NIOS_HOST_MOUSE_VGA Refer to Figure 7.2 and setup the lab according to the following steps: Connect a USB Mouse to the USB Host Connector of the DE2 board.
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Lab 3: USB Paint Brush Figure 7.
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Lab 4: USB Device Chapter Chapter 8 Lab 4: USB Device 8 Most USB applications/products are running as a USB device instead of host. In this lab, we are implementing DE2 as a USB device and we can use Software in PC to control the USB Device (DE2). Design Descriptions 8-1 The DE2 Board also provides a USB Device port for users to connect the DE2 board to a PC using the USB cable.
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Lab 4: USB Device Figure 8.1 The Block Diagram of the USB Device Project Lab Setup and Instructions 8-2 Project Directory: C:\DE2\UP4_NIOS_DEVICE_LED\DE2_ISP1362_DC Bitstream Used: UP4_api.sof or UP4_api.pof NIOSII Workspace: C:\DE2\UP4_NIOS_DEVICE_LED\DE2_ISP1362_DC BC++ Software Driver: C:\DE2\UP4_NIOS_DEVICE_LED Refer to Figure 8.2 and setup the lab according to the following steps: Load the bitstream into FPGA Run NIOSII IDE with DE2_ISP_1362_DC as workspace.
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Lab 4: USB Device Execute the software: “C:\DE2\UP4_NIOS_DEVICE_LED\ ISP1362DcUsb.exe” Click on “ADD” button to increment the number/register shown on the 7-SEG displays. The incremented result is also sent back to PC side using the USB link. Click on “Clear” button to clear the register content. Figure 8.
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Lab 5: A Karaoke Machine Chapter 9 Chapter 9 Lab 5: A Karaoke Machine This lab demonstrates the audio quality of the DE2 Board by using its LINEIN, LINEOUT, and microphone-in circuits in a Karaoke Machine Application implemented on the DE2 board. Design Descriptions 9-1 In this lab, we configure the audio CODEC in the master mode, where the audio CODEC generates AD/DA serial bit clock (BCK) and the left/right channel clock (LRCK) automatically.
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Lab 5: A Karaoke Machine Lab Setup and Instructions 9-2 Project Directory: C:\DE2\DE2_i2sound Bitstream Used: i2sound.sof or i2sound.pof Refer to Figure 9.2 and setup the lab according to the following steps: Connect a microphone to the MIC connector (pink color) of the DE2 board. Connect a MP3/IPOD/PC audio output to the LINEIN connector (blue color) of the DE2 board. Connect a headset/speaker to the LINEOUT connector (green color) of the DE2.
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Lab 6: Ethernet Packet Sending/Receiving Chapter 10 Chapter 10 Lab 6: Ethernet Packet Sending/Receiving Ethernet communication is essential to many digital products such as set-top box and home gateway. In this lab, we will show how to send and receive Ethernet packets using the Fast Ethernet controller on DE2 board. Design Descriptions 10-1 In this project, NIOS II CPU sends and receives Ethernet packets using DM9000A Ethernet PHY/MAC Controller.
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Lab 6: Ethernet Packet Sending/Receiving Figure 10.1 Packet Sending and Receiving using NIOS II CPU Lab Setup and Instructions 10-2 Project Directory: C:\DE2\UP4_NET Bitstream Used: UP4_API.sof or UP4_API.pof NIOSII Workspace: C:\DE2\UP4_NET Refer to Figure 10.2 and setup the lab according to the following steps: Plug in a CAT5 loopback cable into the Ethernet connector of DE2.
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Lab 6: Ethernet Packet Sending/Receiving Figure 10.
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Lab 7: DE2 Control Panel Chapter Chapter 11 11 Lab 7: DE2 Control Panel This chapter will illustrate the DE2 Control Panel package that allows users to control the board using Window GUI menu. This package provides users a simple yet powerful method to control the board. The connection from your PC to the board can be done by USB cable. In this lab, we will teach users how to use the USB version of the DE2 Control Panel Package. Important Note on the USB Link 2.
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Lab 7: DE2 Control Panel read/write the SRAM, Flash Memory, and SDRAM; load a image pattern to display on VGA; load music to memory and play the music via audio DAC. The feature of reading/writing a byte or an entire file from/to the Flash Memory allows users to develop many multimedia applications (Flash Audio Player, Flash Picture Viewer) without worrying about how to build a Flash Memory Programmer. Perform the following steps to repeat the experiments. 1. Figure 6.
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Lab 7: DE2 Control Panel 3. Click Open > Open USB Port 0 (DE2 Control Panel Application will list all the USB ports that connect to DE2 boards. DE2 Control Panel can control up to 4 DE2 boards using the USB links). Note that The Control Panel will occupy the USB port until you close the port – you cannot use Quartus II to download unless you close the USB port. 4. Refer to Figure 11.3. Switch to LED & LCD page. Click on the check boxes of LEDs and click on Set. The corresponding LEDs are lighted up.
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Lab 7: DE2 Control Panel You need to ERASE entire Flash memory before you can write to it. Remember that the number of time a Flash memory can be erased is limited. The time required to erase entire Flash memory is 15 secs - 21 secs. Please do not close the DE2 Control Panel in the middle of operation Follow the steps to exercise the operations to the Flash memory: 1. Click on Button Flash to change to Flash Memory Control Page (Refer to Figure 11.4). Figure 11.4. Flash Memory Control Page 2.
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Lab 7: DE2 Control Panel Figure 11.5. Random Access to the Flash Memory 5. You can also load a file into Flash by using Sequential Write function. Please refer to Figure 11.6. You have to specify the starting address and the length (in bytes) to be written into the Flash. 6. You can click on “File Length” checkbox to indicate that you want to load entire file into the flash memory. Then Click on Write File to Flash to choose the file to be loaded into the flash memory. 7.
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Lab 7: DE2 Control Panel The SDRAM / SRAM Controller and Programmer 11-4 The DE2 Control Panel can serves as a SDRAM Programmer. Users can read/write a 16-bit word from/to the SDRAM, write a binary file to the SDRAM, load the content of the SDRAM to a file. DE2 Control Panel can also controls SRAM using the identical method. Follow the steps to exercise the operations to the SDRAM: 1. Please refer to Figure 11.8. Click on Button SDRAM to switch to SDRAM Control Page. 2.
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Lab 7: DE2 Control Panel Figure 11.8. The SDRAM Controller Panel PS/2 and 7-SEG Display Control 11-5 DE2 Control Panel gives you a control window with associated IP to allow users to input using PS/2 keyboard; the keys pressed on the keyboard will be displayed in the message box of the DE2 Control Panel. DE2 Control Panel also allows users to control the 7-SEG displays on DE2. Figure 11.9 shows the setup of the connection. Figure 11.
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Lab 7: DE2 Control Panel Figure 11.9 PS2 and USB/RS232 connection Setup Figure 11.
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Lab 7: DE2 Control Panel SRAM/SDRAM/Flash. Once the content is downloaded to the SDRAM/Flash, users can configure the memory controllers so that their IP can read/write the SDRAM/Flash via the asynchronous ports connected. Repeat the following steps to exercise the multi-port Flash controller – we will implement a Flash Music Player as example here. Refer to Figure 11.4 and 11.6, use the Flash Programmer to erase the Flash memory and then write a music file into the Flash memory.
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Lab 7: DE2 Control Panel Figure 11.12 DE2 Control Panel – The TOOLS page VGA Display Control Panel – Display Default Image 11-7 DE2 Control Panel provides users a tool with associated IP to display either a default image or user’s own picture on VGA output. Repeat the following steps to display a default image on a VGA monitor. Switch to VGA Control Page by clicking on the VGA tab as shown in Figure 11.13. Make sure the checkboxes of Default Image and Cursor Enable are checked.
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Lab 7: DE2 Control Panel users’ own image data. Figure 11.13 Display default image and use the scrolling bars to control cursor moving VGA Display Control Panel – Display User’s Own Image 11-8 DE2 Control Panel can display users’ own images on VGA monitors. Repeat the following steps to display users’ own picture on a VGA monitor. Switch to SRAM Control Page and load the file C:\ DE2 \ Binary_Raw_Data\ Raw_Data_Gray into SRAM.
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Lab 7: DE2 Control Panel Figure 11.14 Select Asynchronous Port 1 for SRAM so that the image stored in SRAM can be displayed on a VGA monitor Switch to VGA Page and deselect the checkbox of Default Image. You should see the VGA monitor connected to the DE2 board is showing the Raw_Data_Gray stored in SRAM, as shown in Figure 11.15. Users can turn off the green cursor by deselecting the checkbox of Cursor Enable. Figure 11.
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Lab 7: DE2 Control Panel How to Prepare Your Own Image Data 11-9 This section describes how to prepare users’ own image files to be loaded into the external SRAM or internal M4K SRAM and displayed on the monitor connected to the DE2 board. Use any image processing tools such as Corel Photo Paint to load your desired image data. Resample your original image into 640x480 resolution and change the image into 8-bit Grayscale mode. Save the modified image in Window Bitmap format.
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Lab 7: DE2 Control Panel TXT format) for the black&white version of the image – the threshold for judging black or white level is defined in the BW Threshold. Image Source R/G/B Band B&W Output Result Filter Threshold (640x480) Filter Color Picture R/G/B N/A Raw_Data_Gray Color Picture R/G/B BW Threshold Raw_Data_BW + (optional) Grayscale Raw_Data_BW.txt N/A N/A Raw_Data_Gray N/A BW Threshold Raw_Data_BW + Picture Grayscale Picture Raw_Data_BW.txt Note: Raw_Data_BW.
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Lab 8: SD Card Music Player Chapter 12 Chapter 12 Lab 8: SD Card Music Player Many commercial media/audio players use large external storage devices, such as SD card or CF card, to store music/movie files; many new commercial audio/media players have very high-end audio DAC circuits to provide users’ the best sound quality.
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Lab 8: SD Card Music Player Figure 12.1 The Block Diagram of SD Music Player Lab Setup and Instructions 12-2 Project Directory: C:\DE2\UP4_SD_Card_Audio Bitstream Used: UP4_API.sof or UP4_API.pof NIOSII Workspace: C:\DE2\UP4_SD_Card_Audio Refer to Figure 12.2 and setup the lab according to the following steps: Format your SD card into FAT16 format.
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Lab 8: SD Card Music Player Figure 12.
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Appendix Chapter Chapter 13 13 Appendix Revision History 13-1 Date / Author Change Log Aug 30, 2005 Initial Version (Preliminary) for DE2 Sample Demo Sean Peng OCT 02. 2005 Release ready for first DE2 production lot Sean Peng Schematic 13-2 Please send email to support@terasic.com for requesting schematic information. Always Visit DE2 Webpage for New Labs 13-3 We will be continuing providing interesting examples and labs on our DE2 webpage. Please visit www.altera.com or de2.terasic.