User guide

SFSU - Embedded Systems Tutorial Nano- Electronics & Computing Research Lab
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Pixel Converter
VGA Sink
Peripheral Bridge
Sd Card Controller
Interval Timer
Touch Panel
Touch Panel SPI
Touch Panel penirq
Touch Panel Busy
Step 6: Go to the “Connections” column and connect the following ports:
i. Pll_slave(system clock) is connected to cpu, jtag_uart, sysid, sdram, tri_state
bridge flas, cfi_flash, sram, on chip memory, SGDMA Controller, Fifo and
peripheral bridge
j. CPU’s jtag_debug_module to SDRAM, Tristate Bridge, SRAM.
k. SDRAM to SGDMA Controller’s “m_read”.
l. Descriptor Memory to SGDMA Controller’s “Descriptor Read”
m. Descriptor Memory to SGDMA Controller’s “Descriptor Write”
n. SGDMA Controller’s out to Timing Adapter’s “in”.
o. Timing Adapter’s “out” to FIFO’s “in”.
p. FIFO’s “out” to Pixel Converter’s “in”.
q. Pixel Converter’s “out” to VGA_Sink.
r. SD Card Controller to System Clock Timer, Touch Panel SPI, Touch_Panel_irq_n
and Touch_Panel_busy.
s. Open the Nios II processor named CPU and change the reset vector and
exception vectors to onchip_memory2
Step 7: For assignment of base addresses in SOPC Builder:
Click on “Auto assign base addresses” on the main menu bar and “Auto assign IRQ’s” as
shown in figure below: