User guide

SFSU - Embedded Systems Tutorial Nano- Electronics & Computing Research Lab

.VGA_DATA_EN_from_the_video_vga_controller(),

.VGA_G_from_the_video_vga_controller(),

.VGA_HS_from_the_video_vga_controller(),

.VGA_R_from_the_video_vga_controller(),

.VGA_SYNC_from_the_video_vga_controller(),

.VGA_VS_from_the_video_vga_controller()

)

Step 11: This code should be copied and pasted in the main Verilog (shown previously) under REG/WIRE

declarations section. The modifications are shown in green:

system (

// 1) global signals:

.clk_0(CLOCK_50),

.clocks_VGA_CLK_40_out(),

.clocks_VGA_CLK_out(),

.clocks_sys_clk_out(),

.reset_n(SW[17]),

// the_SW

.in_port_to_the_SW(),

// the_video_vga_controller

.VGA_BLANK_from_the_video_vga_controller(),

.VGA_B_from_the_video_vga_controller(B),

.VGA_CLK_from_the_video_vga_controller(LCD_NCLK),

.VGA_DATA_EN_from_the_video_vga_controller(LCD_DEN),

.VGA_G_from_the_video_vga_controller(G),

.VGA_HS_from_the_video_vga_controller(),

.VGA_R_from_the_video_vga_controller(R),