User guide

SFSU - Embedded Systems Tutorial Nano- Electronics & Computing Research Lab

3.3 Overview of System Integration Software SOPC Builder and Q Sys

NOTE: This diagram was taken from Altera’s Nios II Software Developer’s Handbook,

http://www.altera.com/literature/hb/nios2/n2sw_nii5v2.pdf

System Integration Software

This software allows the designer to marry hardware and software. In order to use the Nios II

soft-core processor, a system must be designed using either SOPC builder or QSys (both are

accessed from Quartus II-> Menu -> Tools). QSys is a newer version of SOPC builder and it is

encouraged that students begin with QSys. This development tool primarily generates

the .sopcinfo file which is used in Nios II SBT for Eclipse to create the software project to run on

top of the FPGA design, utilizing the Nios II soft-core processor.

After creating a system to suit the students’ project needs, “Generation” (synonymous to

“Compilation”) automatically creates the necessary hardware files for low-level abstraction. A

main niosII module is created in this process, which is instantiated from the top-level hardware

file. This process is described as System Integration

Although much of the reading presented here applies to SOPC Builder, the information applies

also to QSys and an effort should be made to use QSys in place of SOPC Builder.

1) Introduction to the Altera SOPC Builder:

<system cd>\DE2_115_tutorials\tut_sopc_introduction_verilog.pdf

2) QSys System Design: http://www.altera.com/literature/tt/tt_qsys_intro.pdf

• QSys main reference page: http://www.altera.com/products/software/quartus-

ii/subscription-edition/qsys/qts-qsys.html?GSA_pos=10&WT.oss_r=1&WT.oss=qSys

3) SOPC Builder User Guide: http://www.altera.com/literature/ug/ug_sopc_builder.pdf