Embedded Systems Design Flow using Altera’s FPGA Development Board (DE2115 T-Pad) SPRING 2012 Ankita Goel Hamid Mahmoodi
Table of Contents Chapter 1: Introduction to the DE2-115 Development and Education Board ............................................... 3 1.1 Overview of DE2-115 .......................................................................................................................... 3 1.2 Block Diagram of the DE2-115 Board.................................................................................................. 5 1.3 Getting Started..................................................................
Link to the Video Demonstration:........................................................................................................... 67 Chapter 5 – Integrating Touch Interface of T-Pad ...................................................................................... 68 Introduction ................................................................................................................................................ 68 Step by Step ALU on T-Pad with Touch Interface Tutorial .............
Chapter 1: Introduction to the DE2-115 Development and Education Board 1.1 Overview of DE2-115 This device (FPGA Board) is specifically designed for to create, implement, and test digital designs using programmable logic. Figure below shows the I/O ports in DE2-115. It shows the layout of the board and indicates the location and connections of various components.
Altera Cyclone® IV 4CE115 FPGA device Altera Serial Configuration device – EPCS64 USB Blaster (on board) for programming; both JTAG and Active Serial (AS) programming modes are supported 2MB SRAM Two 64MB SDRAM 8MB Flash memory SD Card socket 4 Push buttons 18 Slide switches 18 Red user LEDs 9 Green user LEDs 50MHz oscillator for clock sources 24-bit CD-quality audio CODEC with line-in, line-out, and microphone-in jacks VGA DAC (8-bit high-speed triple DACs) with VGA-out connector TV Decoder
1.2 Block Diagram of the DE2-115 Board Figure gives the block diagram of the DE2-115 board. To provide maximum flexibility for the user, all connections are made through the Cyclone IV E FPGA device. Thus, the user can configure the FPGA to implement any system design.
•JTAG and AS mode configuration •EPCS64 serial configuration device •On-board USB Blaster circuitry Memory devices: •128MB (32Mx32bit) SDRAM •2MB (1Mx16) SRAM •8MB (4Mx16) Flash with 8-bit mode •32Kb EEPROM SD Card socket: •Provides SPI and 4-bit SD mode for SD Card access Connectors: •Two Ethernet 10/100/1000 Mbps ports •High Speed Mezzanine Card (HSMC) •Configurable I/O standards (voltage levels:3.3/2.5/1.8/1.5V) •USB type A and B Provide host and device controllers compliant with USB 2.
•18 red and 9 green LEDs •Eight 7-segment displays Other features: •Infrared remote-control receiver module •TV decoder (NTSC/PAL/SECAM) and TV-in connector Power: •Desktop DC input •Switching and step-down regulators LM3150MH 1.3 Getting Started After getting the overview of the kit, next step is to download the necessary software development tools and drivers for the DE2-115 that will connect to your host computer via USB.
Step 1) Go to the link below: https://www.altera.com/download/dnl-index.
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Step 4) Select the Destination where the Altera folder is going to be located and the name of the folder Click next SFSU - Embedded Systems Tutorial 10 Nano- Electronics & Computing Research Lab
Step 5) Select everything except for the Components that say “Paid”. The Paid version is a 30-day trial after that you will not be able to use it.
Step 6) Click next for the DSP Builder setup SFSU - Embedded Systems Tutorial 12 Nano- Electronics & Computing Research Lab
Step 7) A summary of what will be installed to the computer will appear SFSU - Embedded Systems Tutorial 13 Nano- Electronics & Computing Research Lab
Step 8) After the installation is complete click finish. Using these steps, Quartus and Nios software can be downloaded and ready to be used on the board.
1.4 Control Panel Demonstration To get familiarized with the board, Control Panel can be used which automatically uses Quartus II to run a demonstration on the DE2-115. A video link demonstrating the same is given below: http://www.youtube.com/watch?v=EtDDd07yUnw Step 1: Connect the DE2-115 to your host computer through the USB port. Turn on pressing the big red push-button. Make sure that SW-19 is set to Run.
Chapter 2: Hardware Design Flow Using Verilog in Quartus II 2.1 Introduction to Quartus II System Development Software This chapter is an introduction to the Quartus II software that will be used for analysis and synthesis of the DE2-115 Development and Education Board. Throughout this chapter hardware description languages like Verilog will be used for coding. The Altera Quartus II design software provides a complete, multiplatform design environment for system-on-a-programmable-chip (SOPC) designs.
a) Design Flow- Introduction (Page No. 11), Graphical User Interface Design Flow (Page No. 12) b) Design Entry (Page No. 29) Introduction, Creating a Project(Page No. 30), Creating a Design(Page No. 31), later this document can be used for a specific method of design entry (like Verilog, Block Diagram, VHDL, etc.) c) Programming & Configuration (Page No. 93) Introduction, Creating and Using Programming Files 2) Using Verilog for Quartus II Design: \DE2_115_tutorials\tut_quartus_intro_verilog.
2.
2.3 Binary Adder Example Now that you are getting familiar with Quartus II and the DE2-11 a tutorial discussing the basic steps for using Quartus II is discussed below. In this example, the components from the DE2-115 Board that will be used are: 7 Segment Hex Display, Switches, 8 Red LEDs, and the LCD Display As shown in the picture above the switches and LED’s are synchronized and represent a 4 bit binary number. The values of these binary numbers are displayed on the 7 segment display and LCD.
0The Binary Adder tutorial teaches how to Connect the conputer with the DE2-115. Create a new project using Quartus II. Create a Verilog file. Put I/O pin locations in the assignment editor. Synthesize your design. Use system builder. 1. The youtube video for the complete procedure can be accessed from the link given below: http://www.youtube.com/watch?v=PB9wk5Wl_Ec 2.
c) Under the tab “Driver” select “Update Driver” -> A new window will pop up and you’ll select “Browse my computer for driver software SFSU - Embedded Systems Tutorial 21 Nano- Electronics & Computing Research Lab
d) In the field “Search for Drivers in this location” browse your computer to create the following path: C: - > Altera -> 11.0 -> Quartus -> Drivers -> USB Blaster then select “Browse” e) You may need to click “allow” to complete the process. Step 2: Open the Quartus II software a) Select “Create New Project Wizard” b) In the first step (1 of 5) you will need to create a directory for your project and name your new project.
c) In step 2 of 5, you will add any previously created files to your project. Make sure to go to the lower portion of screen and select “Add User Libraries”. i. A new window opens. Go to “Global Library Name” and to the right of Global libraries click on “…” ii. Go to “Computer” then go to the “C drive” (where the Altera folder is located) iii. Go to on the Altera folder then go to the “quartus” folder iv. Go to on the “libraries” folder v.
ii. Target device is “Specific” and select our device from “Available Devices”EP4CE115F29C7. Click “Next” e) In step 4 of 5, EDA Tool Settings do not make any adjustments. Click “Next” f) In step 5 of 5, Summary, click “Finish to create your new project. Step 3: You will need to create a new Verilog file for your project.
c) Click “OK” d) A new Verilog file will open. An asterisk will appear near the file name whenever unsaved changes have been made. ~ This tutorial focuses on Verilog (a hardware description language), In order to program the Altera DE2-115 Step 4: Copy the Verilog Code from the file Binary_Adder.txt file into Quartus II Note: Binary_Adder.txt is located in the Codes folder Step 5: You will use the DE2-115 manual to determine ports and PIN assignments.
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Step 6: For any project it is required to create pin assignment from the DE2-115 manual. a) Under “Assignments” select “Assignment Editor” b) Add each port under “Assignment Name” –each port will need two assignments: i. PIN location ii. I/O requirement. Note: This process is very lengthy and in the future can be bypassed using “System Builder”( PG No. 15).
Step 7: When the Verilog code is finished, and all assignments are done, you will be ready to compile your design and program the device. Step 8: At the top of the screen, select the “Play” button to begin the automatic compilation process. Watch in the lower left screen as the compilation process occurs. This may take several minutes. (Step 7) Step 9: When it has compiled, double click on “Program Device”. a) Push the large red button on the FPGA board to turn on the power.
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2.4 Introduction to System Builder Alternate way to do pin assignments with the help of System Builder System builder is a GUI that creates pin assignment by selecting the components that will be needed for a project. System builder saves time by creating the pin assignments for you and letting you choose what components you need. For Example:1) Open DE2_115_tools->DE2_115_system_builder to find DE2_115_SystemBuilder.
4) Click Generate 5) Create a directory for your project and then click save 6) To open this project open the .qpf file 7) Delete the verilog code that System Builder created then copy the code from Binary_Adder_System_Builder(is located in the codes folder) 8) At the top of the screen, select the “Play” button to begin the automatic compilation process. Watch in the lower left screen as the compilation process occurs. This may take several minutes.
9) When it has compiled, double click on “Program Device”. a) Push the large red button on the FPGA board to turn on the power. b) Programmer will open, and at the top left “USB Blaster” will appear. If it does not, click on “Hardware Setup”. Select “USB Blaster” and click ok. c) When “USB Blaster” appears next to “Hardware Setup” select “Start” and watch the upper right corner as the design is implemented. d) When the “Progress” bar has reach 100% you may test your design on the FPGA board.
7 Segment Hex Display SFSU - Embedded Systems Tutorial 35 Nano- Electronics & Computing Research Lab
In this project we used four 7-segment displays to show the values of switches being turned on in binary. In a 7- segment display a high logic level will turn off the led and a low logic level to a segment will turn the led on. To represent an LED with a seven-bit value we use the values zero through six. To display a zero to a segment we set the hex value to be equal to 7b’1000000. This is because a zero will have all led on but the center led (number 6 on the figure above).
16 x 2 LCD SFSU - Embedded Systems Tutorial 37 Nano- Electronics & Computing Research Lab
To display characters to an LCD there is a series of steps that need to be done before to initializing the LCD module. Since Verilog doesn’t read code sequentially we created a case statement that will allow the initialization to be done in order. This is done by changing the state of the case to the next step in every case statement.
LINE, DROP LCD, HOLD, DISPLAY ON, and MODE SET AND PRINT STRING. These reset needs to be done three time to because we need to initialize enable to high and register select and read/write to low signals. These steps are also done to communicate with the LCD to determine if it will be an 8 or 4 bit data bus, this is done by setting the data bus equal to the hex value eight(8’h38).
Chapter 3: Hardware and Software Codesign Flow 3.1 Introduction to Nios II Soft-Core Processor 1) Introduction to the Altera Nios II Soft Processor: \DE2_115_tutorials\tut_nios2_introduction.pdf • focus: All of the information in this resource is needed for creating systems and should be read carefully, as familiarity will greatly help students in avoiding time consuming mistakes. Nios II is an embedded processor architecture designed specifically for Altera’s FPGA boards.
NOTE: This figure taken from Altera’s Nios II Processor Reference Handbook: http://www.altera.com/literature/hb/nios2/n2cpu_nii5v1.pdf page 18 2) Nios II Hardware Development: http://www.altera.com/literature/tt/tt_nios2_hardware_tutorial.pdf • focus: This resource is an excellent overview of the basic requirements to creating a system using QSys in Quartus II, instantiating the design in the project files, implementation, and then creating the necessary software.
3.2 Co-design Flow Figure 1–2 shows the Nios II system development flow between hardware and software. This flow consists of three types of development: hardware design steps, software design steps, and system design steps. NOTE: This figure taken from Altera’s Nios II Hardware Development Tutorial: http://www.altera.com/literature/tt/tt_nios2_hardware_tutorial.
3.3 Overview of System Integration Software SOPC Builder and Q Sys NOTE: This diagram was taken from Altera’s Nios II Software Developer’s Handbook, http://www.altera.com/literature/hb/nios2/n2sw_nii5v2.pdf System Integration Software This software allows the designer to marry hardware and software. In order to use the Nios II soft-core processor, a system must be designed using either SOPC builder or QSys (both are accessed from Quartus II-> Menu -> Tools).
3.4 Introduction to Nios II SBT for Eclipse Eclipse allows the user to use the software that was executed by a Nios II processorbased system in an FPGA. The user can configure the FPGA on the development board with the pre-generated Nios II standard hardware system by downloading the FPGA configuration file to the board. 1) Nios II Software Developer’s Handbook: http://www.altera.com/literature/hb/nios2/n2sw_nii5v2.pdf NOTE: Link is placed here for reference, but is not necessary for review in this stage.
NIOS II Binary Adder Step 1: System Builder 1) Open DE2_115_tools->DE2_115_system_builder to find DE2_115_SystemBuilder.exe 2) Name the project under Project Name: Binary_Adder_Nios 3) Check all Components that you will be using: in this Tutorial we are using CLOCK, LEDx27, 7-Segementx8, Switchx18, and of course the LCD. 4) Click Generate 5) Create a directory for your project and then click save 6) To open this project open the .
Step 2: Building Qsys System 1) Open Qsys under tools tab 2) Start by adding a Nios II Processor Core: Under “Component Library”-> Processors -> Nios II Processor -> Add a. Select “Nios II/s” b. Set “Hardware multiplication type” = “None” c. Disable “Hardware divide” d. “Finish” e. Rename Nios to “cpu” 3) On-Chip Memory: Under “Component Library”-> Memories and Memory Controllers -> On-Chip -> On-Chip Memory (RAM or ROM)-> Click “Add” a. Block Type list = “Auto” b.
10) Go to the “Export” column and connect the following ports: a. Click on “click to export” on the external connection row to activate connection for all of the led’s, switches and 7 segment display. b. Click on “click to export” on the external row for the LCD 11) Under Generation click generate a. Save as “Nios” b. Once generation is complete coping code from HDL example Step 2: Quartus HDL Connections 1) Add IP Variation File: Menu bar: Assignments -> Settings a.
b. Locate and choose the file nios2/synthesis/nios.qip c. Add to project, click okay and close 2) Copy code under structural coding in Quartus (Code located in the Codes folder under Binary_Adder_Quartus) a. Notice LCD_BLON is set to 1'b1; b. Notice LCD_ON is set to 1'b1; c. Notice all connections in parenthesis 3) Compile and Run a.
Step 3: Develop the Software for Nios II SBT for Eclipse 1) This step relies on the .sopcinfo file created when generating the Qsys system 2) Open Nios II SBT for Eclipse a) Indicate workspace as your project directory, and create a new file called “Software” and click “Okay” b) Set perspective to Nios II: Menu -> Window -> Open Perspective -> Other -> Nios II c) Menu -> File -> New -> Nios II Application and BSP from Template i) Under “Target Hardware Information” select file \nios.
4) Build project 5) Run as Hardware SFSU - Embedded Systems Tutorial 50 Nano- Electronics & Computing Research Lab
Chapter 4 : Video Generation for Text Display on T-Pad Introduction In this chapter, the ALU will be displayed on T-Pad. Switches perform different operation of the ALU. With switches, different numbers can be displayed and also their ALU operations can be performed. Hardware Character Buffer DMA The T-Pad features an 8-inch Amorphous-TFT-LCD panel. The LCD Screen module offers resolution of (800x600) to provide users the best display quality for developing applications.
Video Pipeline A Scatter Gather DMA is used to connect to the VGA Controller as shown in the figure below. A summary of how video is fed to the VGA Controller is given in the paragraph below. The Scatter Gather DMA is used for high speed data transfer between two components. It is used to transfer and merge noncontiguous memory to continuous address space and vice versa. It works in three modes. 1. Memory to Memory 2. Memory to Data Stream 3.
Step by Step ALU on T-Pad Tutorial Hardware Setup Step 1 : System Setup by using System Builder Open System Builder, select Clock, LED, VGA and switches as shown in figure below.
Select HSMC Source as LTC – 8” LCD/Touch Camera as shown below. Select a project name, for this example we are using “tpad_alu_display” as our project name Click on Generate and open the folder containing these files. Open the folder where the project files are saved and open tpad_alu_display.qpf file. This file will be opened in quartus II.
SW, //////////// VGA ////////// VGA_B, VGA_BLANK_N, VGA_CLK, VGA_G, VGA_HS, VGA_R, VGA_SYNC_N, VGA_VS, //////////// I2C for HSMC ////////// I2C_SCLK, I2C_SDAT, //////////// HSMC, HSMC connect to LTC - 8" LCD/Touch/Camera ////////// CAMERA_D, CAMERA_FVAL, CAMERA_LVAL, CAMERA_PIXCLK, CAMERA_RESET_N, CAMERA_SCLK, CAMERA_SDATA, CAMERA_STROBE, CAMERA_TRIGGER, CAMERA_XCLKIN, LCD_B, LCD_DEN, LCD_DIM, LCD_G, LCD_NCLK, LCD_R, TOUCH_BUSY, SFSU - Embedded Systems Tutorial 55 Nano- Electronics & Computing Research L
TOUCH_CS_N, TOUCH_DCLK, TOUCH_DIN, TOUCH_DOUT, TOUCH_PENIRQ_N ); //======================================================= // PARAMETER declarations //======================================================= //======================================================= // PORT declarations //======================================================= //////////// CLOCK ////////// input CLOCK_50; input CLOCK2_50; input CLOCK3_50; //////////// LED ////////// output [8:0] LEDG; output [17:0] LEDR; /////////
//////////// I2C for HSMC ////////// output I2C_SCLK; inout I2C_SDAT; //////////// HSMC, HSMC connect to LTC - 8" LCD/Touch/Camera ////////// input [11:0] CAMERA_D; input CAMERA_FVAL; input CAMERA_LVAL; input CAMERA_PIXCLK; output CAMERA_RESET_N; output CAMERA_SCLK; inout CAMERA_SDATA; input CAMERA_STROBE; output CAMERA_TRIGGER; output CAMERA_XCLKIN; output [5:0] LCD_B; output LCD_DEN; output LCD_DIM; output [5:0] output output LCD_G; LCD_NCLK; [5:0] LCD_R; input TOUCH
//======================================================= Endmodule Step 3: SOPC Builder Hardware Setup Open SOPC Builder Window and add: CPU On – Chip memory Character Buffer with DMA Pixel Buffer Pixel Buffer with DMA Pixel RGB Resampler Pixel Scaler Video Clipper Alpha Blender Dual Clock FIFO VGA Controller JTAG UART SYSID Touch Panel SPI Touch Panel penirq Touch Panel Busy Altpll_0 Step 3a: Go to the “Connections” column and connect the following ports: c.
Step 3b: For assignment of base addresses in SOPC Builder: Click on “Auto assign base addresses” on the main menu bar and “Auto assign IRQ’s” as shown in figure below: The complete SOPC Builder system is shown below: SFSU - Embedded Systems Tutorial 59 Nano- Electronics & Computing Research Lab
Note: If you wish to open the complete already designed hardware in SOPC builder, you may open the file “Video_system.sopcinfo” which is attached to this tutorial.
Step 3c: Click on Generate. Step 3(d): After you generate the system. Following code is generated: system ( // 1) global signals: .clk_0(), .clocks_VGA_CLK_40_out(), .clocks_VGA_CLK_out(), .clocks_sys_clk_out(), .reset_n(), // the_SW .in_port_to_the_SW(), // the_video_vga_controller .VGA_BLANK_from_the_video_vga_controller(), .VGA_B_from_the_video_vga_controller(), .VGA_CLK_from_the_video_vga_controller(), .VGA_DATA_EN_from_the_video_vga_controller(), .VGA_G_from_the_video_vga_controller(), .
.VGA_SYNC_from_the_video_vga_controller(), .VGA_VS_from_the_video_vga_controller() ) Step 3(e): This code should be copied and pasted in the main Verilog (shown previously) under REG/WIRE declarations section. The modifications are shown in green: system ( // 1) global signals: .clk_0(CLOCK_50), .clocks_VGA_CLK_40_out(), .clocks_VGA_CLK_out(), .clocks_sys_clk_out(), .reset_n(SW[17]), // the_SW .in_port_to_the_SW(), // the_video_vga_controller .VGA_BLANK_from_the_video_vga_controller(), .
With this step, the hardware simulation is complete. Software Setup This step relies on the .
Basic Software Algorithm Initialize the screen screen_x = 319; screen_y = 239; char text[16]; color = 0x0000; // black color VGA_box (0, 0, screen_x, screen_y, color); // fill the screen with background Values of switches are pointed by allocating their base address volatile int * switch1_ptr = (int *) 0x00101810; volatile int * switch2_ptr = (int *) 0x00101820; volatile int * switch3_ptr = (int *) 0x00101830; volatile int * switch4_ptr = (int *) 0x00101850; According to the switch position, the oper
sprintf (text,"%d & %d = %d ",number1,number2,number1 & number2); } else { sprintf( text_top_VGA, "My ALU"); sprintf (text,"%d | %d = %d ",number1,number2,number1 | number2); } Characters are written on the screen through “VGA_text” function.
Downloading the design to the board: Step 1 –For Hardware, compile the respective .
Step 2 – For software, Run the software program under target as Nios II Hardware shown below: Link to the Video Demonstration: http://www.youtube.
Chapter 5 – Integrating Touch Interface of T-Pad Introduction In this chapter, the ALU will be displayed on T-Pad. Different operation of the ALU is performed by touch interface. With switches, different numbers can be displayed and their ALU operations are performed by touching the buttons on the screen. Hardware Character Buffer DMA The T-Pad features an 8-inch Amorphous-TFT-LCD panel.
Serial Peripheral Interface (SPI) and a Parallel I/0 (PIO) peripheral implement the touch screen interface. The SPI peripheral communicates with the Analog Devices AD7843, touch screen digitizer chip to signal pen_move events. A single PIO captures pen interrupt events, transitions on the pen_down line from the AD7843 chip to indicate pen_down and pen_up events. The Nios II processor in the system runs the software that drives the SPI and PIO peripherals.
Step by Step ALU on T-Pad with Touch Interface Tutorial Step 1 : Open System Builder, select Clock, LED, VGA ans switches as shown in figure below. Step 2 : Select HSMC Source as LTC – 8” LCD/Touch Camera as shown below. Step 3 : Select a project name, for this example we are using “tpad_alu_display” as our project name Click on Generate and open the folder containing these files.
Step 4 : Open the folder where the project files are saved and open “tpad_alu_display.qpf” file. This file will be opened in quartus II.
//////////// I2C for HSMC ////////// I2C_SCLK, I2C_SDAT, //////////// HSMC, HSMC connect to LTC - 8" LCD/Touch/Camera ////////// CAMERA_D, CAMERA_FVAL, CAMERA_LVAL, CAMERA_PIXCLK, CAMERA_RESET_N, CAMERA_SCLK, CAMERA_SDATA, CAMERA_STROBE, CAMERA_TRIGGER, CAMERA_XCLKIN, LCD_B, LCD_DEN, LCD_DIM, LCD_G, LCD_NCLK, LCD_R, TOUCH_BUSY, TOUCH_CS_N, TOUCH_DCLK, TOUCH_DIN, TOUCH_DOUT, TOUCH_PENIRQ_N ); //======================================================= SFSU - Embedded Systems Tutorial 72 Nano- Electronics
// PARAMETER declarations //======================================================= //======================================================= // PORT declarations //======================================================= //////////// CLOCK ////////// input CLOCK_50; input CLOCK2_50; input CLOCK3_50; //////////// LED ////////// output [8:0] LEDG; output [17:0] LEDR; //////////// SW ////////// input [17:0] SW; //////////// VGA ////////// output [7:0] VGA_B; output VGA_BLANK_N; output VG
output I2C_SCLK; inout I2C_SDAT; //////////// HSMC, HSMC connect to LTC - 8" LCD/Touch/Camera ////////// input [11:0] CAMERA_D; input CAMERA_FVAL; input CAMERA_LVAL; input CAMERA_PIXCLK; output CAMERA_RESET_N; output CAMERA_SCLK; inout CAMERA_SDATA; input CAMERA_STROBE; output CAMERA_TRIGGER; output CAMERA_XCLKIN; output [5:0] LCD_B; output LCD_DEN; output LCD_DIM; output [5:0] output output LCD_G; LCD_NCLK; [5:0] LCD_R; input TOUCH_BUSY; output TOUCH_CS_N; output
//======================================================= // Structural coding //======================================================= Endmodule Step 6: Open SOPC Builder Window and add: CPU On – Chip memory Character Buffer with DMA Pixel Buffer Pixel Buffer with DMA Pixel RGB Resampler Pixel Scaler Video Clipper Alpha Blender Dual Clock FIFO VGA Controller JTAG UART SYSID Touch Panel SPI Touch Panel penirq Touch Panel Busy Altpll_0 SFSU - Embedded Systems Tutorial 75 Nano- E
Step 7: Go to the “Connections” column and connect the following ports: f. For all the components connect the clock input and outputs to clock_50 g. For all the components connect the Avalon memory mapped slave to the On-chip memory AMMS. h.
Note: If you wish to open the complete already designed hardware in SOPC builder, you may open the file “Video_system.sopcinfo” which is attached to this tutorial.
Step 9 : Click on Generate. Step 10 : After you generate the system. Following code is generated: system ( // 1) global signals: .clk_0(), .clocks_VGA_CLK_40_out(), .clocks_VGA_CLK_out(), .clocks_sys_clk_out(), .reset_n(), // the_SW .in_port_to_the_SW(), // the_video_vga_controller .VGA_BLANK_from_the_video_vga_controller(), .VGA_B_from_the_video_vga_controller(), .
.VGA_DATA_EN_from_the_video_vga_controller(), .VGA_G_from_the_video_vga_controller(), .VGA_HS_from_the_video_vga_controller(), .VGA_R_from_the_video_vga_controller(), .VGA_SYNC_from_the_video_vga_controller(), .VGA_VS_from_the_video_vga_controller() ) Step 11: This code should be copied and pasted in the main Verilog (shown previously) under REG/WIRE declarations section. The modifications are shown in green: system ( // 1) global signals: .clk_0(CLOCK_50), .clocks_VGA_CLK_40_out(), .
.VGA_SYNC_from_the_video_vga_controller(), .VGA_VS_from_the_video_vga_controller() ) Step 12: Compile and run the system. With this step, the hardware simulation is complete. Software Setup This step relies on the .sopcinfo file created when generating the SOPC System Buider system.
SOFTWARE Algorithm Values of switches are pointed by allocating their base address volatile int * switch1_ptr = (int *) 0x0b081040; volatile int * switch2_ptr = (int *) 0x0b081060; For displaying different options on the LCD Display : sprintf(szText," + "); vid_print_string_alpha(rcPlus.left+5, rcPlus.top, COLOR_WHITE, COLOR_BLACK, tahomabold_32, display, szText); vid_draw_round_corner_box ( rcPlus.left, rcPlus.top, rcPlus.right, rcPlus.
For touch display, different cases are referred for each option selected, which is discussed in the next section. alt_touchscreen_get_pen(screen, (&pen_data.pen_down), (&pen_data.x), (&pen_data.y)); if (PtInRect(&rcPlus, pen_data.x, pen_data.y)){ select = 0; } if (PtInRect(&rcMinus, pen_data.x, pen_data.y)){ select = 1; } if (PtInRect(&rcAnd, pen_data.x, pen_data.y)){ select = 2; } if (PtInRect(&rcOr, pen_data.x, pen_data.y)){ select = 3; } For different ALU options, case statements are used.
szText); break; case 3: result = number1 | number2; sprintf (szText,"%d (|) %d = %d ",number1,number2,result); printf ("%d | %d = %d ",number1,number2,result); vid_print_string_alpha(400, 300, COLOR_WHITE, COLOR_BLACK, tahomabold_20, display, szText); break; } THE LCD Display screen is updated. alt_video_display_register_written_buffer( display ); while(alt_video_display_buffer_is_available(display) != 0); You can obtain the software code by opening the main.c file which is attached with this tutorial.
b) – For software, Run the software program under target as Nios II Hardware shown below: SFSU - Embedded Systems Tutorial 84 Nano- Electronics & Computing Research Lab
Link of Video Demonstration http://www.youtube.
Chapter 6: Video Generation for Text and Image Display on T-Pad Introduction In this chapter, the ALU will be displayed on T-Pad with an image in the background. Terasic T-Pad provides a touch screen, which enables us to incorporate a video component. The strong multimedia capabilities of the T-Pad are used to develop an application that would ease the process of viewing an image from a SD Card.
The hardware can be broken down in the following subsystems. 1. Memory Subsystem 2. Video Pipeline Subsystem 3. Touch Panel Subsystem Memory Subsystem The FPGA provides multiple options for memory storage. It provides on chip memory, off chip SRAM FLASH and SDRAM and a SD Card SPI interface. In this chapter, SDRAM is used as a source for the Scatter Gather DMA for VGA controller. SRAM is not used for this particular design.
SFSU - Embedded Systems Tutorial 88 Nano- Electronics & Computing Research Lab
Step by Step ALU with image in background Tutorial Hardware Setup Step 1 : Open System Builder, select Clock, SDRAM, SRAM, FLASH, SD CARD, VGA and LTC – 8” LCD/Touch/Camera as shown in figure below. Step 2 : Select a project name, for this example we are using “picture_alu” as our project name. Click on Generate and open the folder containing these files. Step 3: Open the folder where the project files are saved and open picture_alu.qpf file. This file is generated when we generate in the above step.
// This code is generated by Terasic System Builder //======================================================= module picture_alu( //////////// CLOCK ////////// CLOCK_50, CLOCK2_50, CLOCK3_50, //////////// LCD ////////// LCD_BLON, LCD_DATA, LCD_EN, LCD_ON, LCD_RS, LCD_RW, //////////// SDCARD ////////// SD_CLK, SD_CMD, SD_DAT, SD_WP_N, //////////// VGA ////////// VGA_B, VGA_BLANK_N, VGA_CLK, VGA_G, VGA_HS, VGA_R, VGA_SYNC_N, SFSU - Embedded Systems Tutorial 90 Nano- Electronics & Computing Research La
VGA_VS, //////////// I2C for HSMC ////////// I2C_SCLK, I2C_SDAT, //////////// SDRAM ////////// DRAM_ADDR, DRAM_BA, DRAM_CAS_N, DRAM_CKE, DRAM_CLK, DRAM_CS_N, DRAM_DQ, DRAM_DQM, DRAM_RAS_N, DRAM_WE_N, //////////// SRAM ////////// SRAM_ADDR, SRAM_CE_N, SRAM_DQ, SRAM_LB_N, SRAM_OE_N, SRAM_UB_N, SRAM_WE_N, //////////// Flash ////////// FL_ADDR, FL_CE_N, FL_DQ, FL_OE_N, SFSU - Embedded Systems Tutorial 91 Nano- Electronics & Computing Research Lab
FL_RST_N, FL_RY, FL_WE_N, FL_WP_N, //////////// HSMC, HSMC connect to LTC - 8" LCD/Touch/Camera ////////// CAMERA_D, CAMERA_FVAL, CAMERA_LVAL, CAMERA_PIXCLK, CAMERA_RESET_N, CAMERA_SCLK, CAMERA_SDATA, CAMERA_STROBE, CAMERA_TRIGGER, CAMERA_XCLKIN, LCD_B, LCD_DEN, LCD_DIM, LCD_G, LCD_NCLK, LCD_R, TOUCH_BUSY, TOUCH_CS_N, TOUCH_DCLK, TOUCH_DIN, TOUCH_DOUT, TOUCH_PENIRQ_N ); //======================================================= // PARAMETER declarations SFSU - Embedded Systems Tutorial 92 Nano- Electron
//======================================================= //======================================================= // PORT declarations //======================================================= //////////// CLOCK ////////// input CLOCK_50; input CLOCK2_50; input CLOCK3_50; //////////// LCD ////////// output inout LCD_BLON; [7:0] LCD_DATA; output LCD_EN; output LCD_ON; output LCD_RS; output LCD_RW; //////////// SDCARD ////////// output SD_CLK; inout SD_CMD; inout [3:0] input SD_DAT
output [7:0] VGA_R; output VGA_SYNC_N; output VGA_VS; //////////// I2C for HSMC ////////// output I2C_SCLK; inout I2C_SDAT; //////////// SDRAM ////////// output [12:0] DRAM_ADDR; output [1:0] DRAM_BA; output DRAM_CAS_N; output DRAM_CKE; output DRAM_CLK; output DRAM_CS_N; inout [31:0] DRAM_DQ; output [3:0] DRAM_DQM; output DRAM_RAS_N; output DRAM_WE_N; //////////// SRAM ////////// output [19:0] output inout SRAM_ADDR; SRAM_CE_N; [15:0] SRAM_DQ; output SRAM_LB_N; out
inout [7:0] FL_DQ; output FL_OE_N; output FL_RST_N; input FL_RY; output FL_WE_N; output FL_WP_N; //////////// HSMC, HSMC connect to LTC - 8" LCD/Touch/Camera ////////// input [11:0] CAMERA_D; input CAMERA_FVAL; input CAMERA_LVAL; input CAMERA_PIXCLK; output CAMERA_RESET_N; output CAMERA_SCLK; inout CAMERA_SDATA; input CAMERA_STROBE; output CAMERA_TRIGGER; output CAMERA_XCLKIN; output [5:0] LCD_B; output LCD_DEN; output LCD_DIM; output [5:0] output output LCD_G; LC
//======================================================= // REG/WIRE declarations //======================================================= //======================================================= // Structural coding //======================================================= endmodule This step initiates all the ports selected on system builder. Step 5: Open SOPC Builder Window and add the following components from library (detailed procedure is explained in chapter no.
Pixel Converter VGA Sink Peripheral Bridge Sd Card Controller Interval Timer Touch Panel Touch Panel SPI Touch Panel penirq Touch Panel Busy Step 6: Go to the “Connections” column and connect the following ports: i. Pll_slave(system clock) is connected to cpu, jtag_uart, sysid, sdram, tri_state bridge flas, cfi_flash, sram, on chip memory, SGDMA Controller, Fifo and peripheral bridge j. CPU’s jtag_debug_module to SDRAM, Tristate Bridge, SRAM. k. SDRAM to SGDMA Controller’s “m_read”. l.
The complete SOPC Builder system is shown below: SFSU - Embedded Systems Tutorial 98 Nano- Electronics & Computing Research Lab
If you wish to open the complete already designed hardware in SOPC builder, you may open the file “nios_simple.sopcinfo” which is attached to this tutorial.
assign reset_n = 1'b1; assign HC_DIM = 1'b1; nios_simple nios_simple_ins( // 1) global signals: .clk_ext(CLOCK_50), .reset_n(reset_n), //.altpll_25(), // .altpll_io(), .clk_sdram(DRAM_CLK), //.clk_sdram(DRAM_CLK), //.clk_pixel(HC_NCLK), ////VGA SINK .vga_b_from_the_vga_source (wire_HC_B), .vga_clk_from_the_vga_source (HC_NCLK), .vga_de_from_the_vga_source (HC_DEN), .vga_g_from_the_vga_source (wire_HC_G), .vga_hs_from_the_vga_source (), .vga_r_from_the_vga_source (wire_HC_R), .
.spi_cs_n_from_the_sd_card_controller (SD_DAT[3]), .spi_data_in_to_the_sd_card_controller (SD_DAT[0]), .spi_data_out_from_the_sd_card_controller (SD_CMD), ////cfi flash .tri_state_bridge_flash_address (FL_ADDR), .tri_state_bridge_flash_data (FL_DQ), .write_n_to_the_cfi_flash (FL_WE_N), .read_n_to_the_cfi_flash (FL_OE_N), .select_n_to_the_cfi_flash (FL_CE_N), ////touch panel interface .MISO_to_the_touch_panel_spi (HC_ADC_DOUT), .MOSI_from_the_touch_panel_spi (HC_ADC_DIN), .
// FLASH_RY, /////////////////////////////////////////// // LCD config assign LCD_BLON = 0; // not supported assign LCD_ON = 1'b1; // alwasy on This code should be copied and pasted in the main Verilog (shown previously) under REG/WIRE declarations section. With this step our hardware configuration is done. After this step, open Nios II IDE Eclipse and write software to configure software of the demonstration. Software Setup Basic Algorithm: 1) Display is initialized.
//vid_draw_round_corner_box ( 300, 400, 500, 500,10, 0x5555, 0x0000, display_global); 4) After the touch is selected , pixel buffer and character buffer gets updated.
touch = 1; x=0; y=0; result = write_buffer(display_global,name_list[pic_index],frame_write_index); sprintf(text_calc,"10 + 5 = 15"); vid_print_string_alpha(350, 410, COLOR_WHITE, COLOR_BLACK, tahomabold_20, display_global, text_calc); sprintf(text_disp,"ADDITION"); vid_print_string_alpha(50, 200, COLOR_WHITE, COLOR_BLACK, tahomabold_20, display_global, text_disp); sprintf(text_disp,"SUBTRACTION"); vid_print_string_alpha(200, 200, COLOR_WHITE, COLOR_BLACK, tahomabold_20, display_global, text_disp); sprintf(
b) – For software, Run the software program under target as Nios II Hardware shown below: SFSU - Embedded Systems Tutorial 105 Nano- Electronics & Computing Research Lab
Video Demonstration of this tutorial is available on YouTube by clicking here: http://www.youtube.
