User guide
6–10 Chapter 6: Board Test System
Using the Board Test System
Cyclone III FPGA Development Kit User Guide September 2010 Altera Corporation
The DDR2 Tab
The DDR2 tab allows you to read and write to one of two DDR2 memory ports on
your board. The DDR2 memory configuration is divided into top design
(implemented by DDR2 chip U11, U12, U13) and bottom design (implemented by
DDR2 chip U25, U26). Figure 6–6 shows the DDR2 tab when the board is configured
with DDR2 top design.
The following sections describe the controls on the DDR2 tab.
Start
The Start control initiates DDR2 memory transaction performance analysis.
Stop
The Stop control terminates transaction performance analysis.
Figure 6–6. The DDR2 Tab