Specifications

Chapter 2: Board Components 2–11
MAX II CPLD
© March 2009 Altera Corporation Cyclone III 3C120 Development Board Reference Manual
K2 2.5 V Output MAX_USER
K15 1.8 V Input MAX_WEn
H12 1.8 V Input MAX2_CLK
M1 2.5 V Input MAXGP_JTAG_TCK
L4 2.5 V Output MAXGP_JTAG_TDI
L5 2.5 V Input MAXGP_JTAG_TDO
M2 2.5 V Input MAXGP_JTAG_TMS
N13 1.8 V Input MWATTS_MAMPS
H13 1.8 V Input PGM[0]
H15 1.8 V Input PGM[1]
H14 1.8 V Input PGM[2]
G16 1.8 V Input PGM[3]
J1 2.5 V Output PMON_CLK
J2 2.5 V Output PMON_CSN
H3 2.5 V Bidir PMON_DATA
H4 2.5 V Output PMON_SDI
H5 2.5 V Output PMON_SYNC
F6 2.5 V Output PWR_DIG_SEL[1]
F1 2.5 V Output PWR_DIG_SEL[2]
G3 2.5 V Output PWR_DIG_SEL[3]
G2 2.5 V Output PWR_DIG_SEL[4]
D2 2.5 V Output PWR_SEG_A
E5 2.5 V Output PWR_SEG_B
D1 2.5 V Output PWR_SEG_C
F3 2.5 V Output PWR_SEG_D
F5 2.5 V Output PWR_SEG_DP
E2 2.5 V Output PWR_SEG_E
F4 2.5 V Output PWR_SEG_F
E1 2.5 V Output PWR_SEG_G
F2 2.5 V Output PWR_SEG_MINUS
G4 2.5 V Input PWR_SEL[0]
G1 2.5 V Input PWR_SEL[1]
G5 2.5 V Input PWR_SEL[2]
H2 2.5 V Input PWR_SEL[3]
D13 — — RESERVED_INPUT
E14 — — RESERVED_INPUT
E15 — — RESERVED_INPUT
G12 — — RESERVED_INPUT
G14 — — RESERVED_INPUT
Table 2–5. MAX II Device Pin-Out (Note 1) (Part 5 of 8)
MAX II Pin Number I/O Standard Signal Direction
Schematic
Signal Name