Specifications

2–10 Chapter 2: Board Components

MAX II CPLD

Cyclone III 3C120 Development Board Reference Manual © March 2009 Altera Corporation

L10 GNDINT Gnd —

A1 GNDIO Gnd —

A16 GNDIO Gnd —

B2 GNDIO Gnd —

B15 GNDIO Gnd —

G7 GNDIO Gnd —

G8 GNDIO Gnd —

G9 GNDIO Gnd —

G10 GNDIO Gnd —

K7 GNDIO Gnd —

K8 GNDIO Gnd —

K9 GNDIO Gnd —

K10 GNDIO Gnd —

R2 GNDIO Gnd —

R15 GNDIO Gnd —

T1 GNDIO Gnd —

T16 GNDIO Gnd —

J13 1.8 V Input HSMA_BYPASS

M4 2.5 V Output HSMA_JTAG_TDI

K4 2.5 V Input HSMA_JTAG_TDO

H16 1.8 V Input HSMB_BYPASS

H1 2.5 V Output HSMAB_JTAG_TDI

B9 2.5 V Input HSMB_JTAG_TDO

E16 1.8 V Input JTAG_SEL

D9 2.5 V Output LCD_BS1

N16 1.8 V Output LCD_SERn

L16 1.8 V Input MAX_CSn

N14 1.8 V Input MAX_DIP[0]

M13 1.8 V Input MAX_DIP[1]

N15 1.8 V Input MAX_DIP[2]

L14 1.8 V Input MAX_DIP[3]

J5 2.5 V Output MAX_EMB

M8 1.8 V Input MAX_EN

J4 2.5 V Output MAX_ERROR

J3 2.5 V Output MAX_FACTORY

K1 2.5 V Output MAX_LOAD

K13 1.8 V Input MAX_OEn

M14 1.8 V Input MAX_RESERVE[0]

P14 1.8 V Input MAX_RESERVE[1]

Table 2–5. MAX II Device Pin-Out (Note 1) (Part 4 of 8)

MAX II Pin Number I/O Standard Signal Direction

Schematic

Signal Name