User guide

ADM-XRC-5T2-ADV User Manual
ADM-XRC-5T2-ADV User Manual
4.1. Local Bus
The ADM-XRC-5T2-ADV implements a multi-master local bus between the bridge and the
target FPGA using a 32- or 64-bit multiplexed address and data path. The bridge design is
asynchronous and allows the local bus to be run faster or slower than the PCI bus clock to
suit the requirements of the user design.
Figure 2 Local Bus Interface
Signal Type Purpose
lad[63:0] bidir Address and data bus.
lbe_l[7:0] bidir Byte qualifiers
lads_l bidir Indicates address phase
lblast_l bidir Indicates last word
lbterm_l bidir Indicates ready and requests new address phase
lready_l bidir Indicates that target accepts or presents new data
lwrite bidir Indicates a write transfer from master
ldreq_l[3:0] unidir DMA request from target to bridge
ldack_l[3:0] unidir DMA acknowledge from bridge to target
fhold unidir Target bus request
fholda unidir Bridge bus acknowledge
lreset_l unidir Reset to target
lclk unidir Clock to synchronise bridge and target
Table 1 Local Bus Interface Signal List
Version 1.0
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