User guide

ManualsBrandsAlpha Data ManualsComputer equipmentADM-XRC-5T2-ADV

Table Of Contents

ADM-XRC-5T2-ADV

PCI Mezzanine Card

• JPEG2000 Video Compression

• Multi-Gigabit Serial I/O

User Guide

Version 1.0

Summary of content (21 pages)

PAGE 1
ADM-XRC-5T2-ADV PCI Mezzanine Card • JPEG2000 Video Compression • Multi-Gigabit Serial I/O User Guide Version 1.
PAGE 3
ADM-XRC-5T2-ADV User Manual Table of Contents 1. 2. 3. 4. 5. Introduction ........................................................................................................................1 1.1. Specifications ............................................................................................................1 Hardware Installation .........................................................................................................2 2.1. Motherboard requirements........................
PAGE 4
ADM-XRC-5T2-ADV User Manual Table of Tables Table 1 Local Bus Interface Signal List .................................................................................... 4 Table 2 Voltage and Temperature Monitors............................................................................. 5 Table 3 MGT Clock Connections ............................................................................................. 8 Table 4 User FPGA I/O Bank Voltages ..........................................................
PAGE 5
ADM-XRC-5T2-ADV User Manual 1. Introduction The ADM-XRC-5T2-ADV is a high performance PCI Mezzanine Card (PMC) designed for supporting development of applications using the Virtex-5 FF1738 Family of FPGA Devices. • Virtex5 LXT: LX110T, LX155T, LX220T or LX330T • Virtex 5 SXT: SX240T • Virtex 5 FXT: FX100T, FX130T, or FX200T The card uses an FPGA PCI bridge developed by Alpha-Data supporting PCI-X and PCI. A high-speed multiplexed address/data bus connects the bridge to the target (user) FPGA.
PAGE 6
ADM-XRC-5T2-ADV User Manual 2. Hardware Installation This chapter explains how to install the ADM-XRC-5T2-ADV onto a PMC motherboard. 2.1. Motherboard requirements The ADM-XRC-5T2-ADV is a 3.3V only PCI device and is not compatible with systems that use 5V PCI signalling levels. The board must be installed in a PMC motherboard that supplies +5.0V and +3.3V power to the PMC connectors. Ensure that the motherboard satisfies this requirement before powering it up. 2.2.
PAGE 7
ADM-XRC-5T2-ADV User Manual 4. Board Description The ADM-XRC-5T2-ADV follows the architecture of the ADM-XRC series and decouples the “target” FPGA from the PCI interface, allowing user applications to be designed with minimum effort and without the complexity of PCI design. A separate Bridge / Control FPGA interfaces to the PCI bus and provides a simple Local Bus interface to the target FPGA.
PAGE 8
ADM-XRC-5T2-ADV User Manual 4.1. Local Bus The ADM-XRC-5T2-ADV implements a multi-master local bus between the bridge and the target FPGA using a 32- or 64-bit multiplexed address and data path. The bridge design is asynchronous and allows the local bus to be run faster or slower than the PCI bus clock to suit the requirements of the user design.
PAGE 9
ADM-XRC-5T2-ADV User Manual 4.2. Flash Memory The ADM-XRC-5T2-ADV is fitted with two separate Flash memories: one connected to the Bridge / Control FPGA and the other to the User FPGA. 4.2.1. Board Control Flash An Intel PC28F256P30 flash memory is used for storing a configuration bitstream for the User FPGA. Once the Bridge / Control FPGA is configured, it checks for a valid bitstream in flash and if present, automatically loads it into the User FPGA.
PAGE 10
ADM-XRC-5T2-ADV User Manual The ‘sysmon’ application is provided upon request that permits the reading of the health monitor. The typical output of the monitor is shown below, provided by the SYSMON program. *** SysMon *** FPGA Space Base Adr = 00900000 Control Space Base Adr = 00d00000 +1V0 +1V2 +1V8 +2V5 +3V3 +5V Pn4 +1V5 Reading Reading Reading Reading Reading Reading Reading Reading = = = = = = = = 1.01 1.21 1.81 2.51 3.32 5.04 3.31 1.51 SysMon Int Temp = User FPGA Temp = V V V V V V V V 33 deg.
PAGE 11
ADM-XRC-5T2-ADV User Manual 4.5. Clocks The ADM-XRC-5T2-ADV is provided with numerous clock sources, as shown in Figure 4 below: PCI Bus PCI RefClk PCI-X CLK Bridge Config (Coolrunner) Bridge FPGA (V4LX25) PCI CLK Zero-delay Buffer (PLL) XTAL_CLK REFCLK_200M 25.0 MHz XTAL 26.5625 MHz XTAL Ctl Femto-clock ICS843034-01 LCLK 200 MHz Osc. Local Bus USERMGT_CLKB USERMGT_CLKA PCIe_RefClk (100 MHz) FCN_MGTREF 156.25 MHz Osc.
PAGE 12
ADM-XRC-5T2-ADV User Manual 4.5.2. REFCLK In order to make use of the IODELAY features of Virtex™-5, a stable low-jitter clock source is required to provide the base timing for tap delay lines in each IOB in the User FPGA. The ADM-XRC-5T2-ADV is fitted with a 200MHz LVPECL (LVDS optional) oscillator connected to global clock resource pins. This reference clock can also be used for application logic if required. 4.5.3.
PAGE 13
ADM-XRC-5T2-ADV User Manual The clock buffer has a PLL with a minimum input frequency of 24MHz, potentially causing problems in applications that use the PCI 33MHz mode with a slow clock. In this case, the buffer can be bypassed to provide full PCI 33MHz compatibility. 4.6. User FPGA 4.6.1. Configuration The ADM-XRC-5T2-ADV performs configuration from the host at high speed using SelectMAP. The FPGA may also be configured from flash or by JTAG via header J2.
PAGE 14
ADM-XRC-5T2-ADV User Manual 4.6.2. I/O Bank Voltages Bank 0 1, 4, 5, 6 2 3 19, 21, 23, 25 27, 29, 31, 33 18 11, 13, 15, 17, 26 12, 20, 24 Voltage 3.3V 1.5V 3.3V 3.3V 1.8V 1.8V 2.5V or 3.3V 3.3V 1.8V Description Configuration I/F DDRII SRAM SelectMAP I/F, Serial Flash Clocks DDRII DRAM DDRII DRAM (LX330T only) Pn4 Interface ADV212 Interface Local Bus Table 4 User FPGA I/O Bank Voltages 4.6.3.
PAGE 15
ADM-XRC-5T2-ADV User Manual 4.7. FCN Interface – MGT Links Eight lanes of user MGT (GTP) links are routed to the front panel connectors. Lanes 0 – 3 are routed through J5, lanes 4 - 7 are routed through J4.
PAGE 16
ADM-XRC-5T2-ADV User Manual 4.7.2.1. Important Notes on using Optical Modules Optical modules provide a signal (‘sense_l’) indicating that they are present; however the presence of optical modules cannot be distinguished from a copper connection by relying on this signal alone.
PAGE 17
ADM-XRC-5T2-ADV User Manual 4.8. Pn4 I/O Up to 16 pairs of differential or 32 single-ended signals are available on Pn4 and are sourced from Bank 18 of the User FPGA. All of the signal traces are routed as 100 Ohm differential pairs and each pair is matched in length. The worst case difference in trace length between any two pairs is 10mm.
PAGE 18
ADM-XRC-5T2-ADV User Manual Signal PCIE_TX0_P PCIE_TX0_N PCIE_RX0_P PCIE_RX0_N PCIE_TX1_P PCIE_TX1_N PCIE_RX1_P PCIE_RX1_N PCIE_TX2_P PCIE_TX2_N PCIE_RX2_P PCIE_RX2_N PCIE_TX3_P PCIE_TX3_N PCIE_RX3_P PCIE_RX3_N PCIE_TX4_P PCIE_TX4_N PCIE_RX4_P PCIE_RX4_N PCIE_TX5_P PCIE_TX5_N PCIE_RX5_P PCIE_RX5_N PCIE_TX6_P PCIE_TX6_N PCIE_RX6_P PCIE_RX6_N PCIE_TX7_P PCIE_TX7_N PCIE_RX7_P PCIE_RX7_N FPGA Pin AB2 AC2 AC1 AD1 AG2 AF2 AF1 AE1 AH2 AJ2 AJ1 AK1 AN2 AM2 AM1 AL1 AP2 AR2 AR1 AT1 AW2 AV2 AV1 AU1 BA1 BA2 BB2 BB3 BA
PAGE 19
ADM-XRC-5T2-ADV User Manual Individual signals to each ADV212 codec ack_l - ADV212 acknowledge signal cs_l - ADV212 chip select signal dack_l<0> to <1> - ADV212 DMA acknowledge signals dreq_l<0> to <1> - ADV212 DMA request signals irq_l - ADV212 interrupt request signal rd_l - ADV212 read enable for host interface operation we_l - ADV212 write enable for host interface operation vdat<0> to <11> - ADV212 video data bus scom4 - ADV212 LCODE Output in Encode Mode 4.10.2.
PAGE 20
ADM-XRC-5T2-ADV User Manual Individual Codec Signals vdat<0> vdat<1> vdat<2> vdat<3> vdat<4> vdat<5> vdat<6> vdat<7> vdat<8> vdat<9> vdat<10> vdat<11> dack_l<0> dack_l<1> dreq_l<0> dreq_l<1> irq_l scomm4 cs_l rd_l we_l ack_l 5.
PAGE 21
ADM-XRC-5T2-ADV User Manual 5.1. Revision History Date Revision Nature of Change 16-Dec-2008 1.0 Initial version ADM-XRC-5T2-ADV User Manual Version 1.