Instruction manual

AVT Prosilica GE Technical Manual V2.0.0
43
VDD-3.3
LOGIC TXD
ISO+5V
MAX3221CPWR
MAXI M
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
EN
C1+
V+
C1-
C2+
C2-
V-
RIN ROUT
INVALID
DIN
FORCEON
DOUT
GND
VCC
FORCEOFF
ISO+5V
SYNC OUT 1
LOGIC TRIGGER INPUT
ISO_+5V
SN74ACT244PWR
TEXAS INSTRU MEN TS
3
5
7
9
12
14
16
18
17
15
13
11
8
6
4
2
20
19
10
1
2Y4
2Y3
2Y2
2Y1
1Y4
1Y3
1Y2
1Y1
2A4
2A3
2A2
2A1
1A4
1A3
1A2
1A1
VCC
2OE
GND
1OE
IN
TRIGGER INPUT
MIN I -SMB
ISO+5V
0.1u
IL716-3
NVE
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
VDD1
GND1
IN1
IN2
OUT3
OUT4
NC
GND1GND2
NC
IN4
IN3
OUT2
OUT1
GND2
VDD2
ISO TXD
ISO+5V
GALVANIC
ISOLATION
BOUNDARY
ISOLATED 5V POWER
RS-232 TXD
SYNC OUT 3
LOGIC SYNC OUT 3
ISO RXD
OUT
SYNC OUT 1
SYNC OUT 2
1
2
3
4
5
6
7
8
9
10
1112
HIROSE HR10A-10R-12SB
1
2
3
4
5
6
7
8
9
10
11
12
0.1u
LOGIC RXD
MIN I -SMB
RS232-TXD
TRIGGER INPUT
SYNC OUT 2
IL716-3
NVE
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
VDD1
GND1
IN1
IN2
OUT3
OUT4
NC
GND1GND2
NC
IN4
IN3
OUT2
OUT1
GND2
VDD2
SYNC OUT 3
TRIGGER INPUT
ISOLATED GROUND
LOGIC SYNC OUT 2
AS SEEN FROM
CAMERA REAR
VIEW
VDD-3.3
RS-232 RXD
ISO+5V
RS232-RXD
0.1u
LOGIC SYNC OUT 1
0.1u
CAMERA INTERNAL CIRCUIT
Camera I/O connector internal circuit diagram
Maxim MAX3221CPWR
Used to drive the RS232 signal logic via the external connector
Texas Instruments SN74ACT244PWR
Used as trigger buffer/driver. The required trigger input current is less
than 10uA and the maximum sync output current is 24mA.
Figure 27: Prosilica GE internal circuit diagram