Specifications

24 Rapier Series Switch
C613-03020-00 REV N
For more information about installing PICs, see the Port Interface Card
Installation and Safety Guide, which is included with every PIC or can be
downloaded from www.alliedtelesis.com/support/software.
For more information about the hardware features of PICs, WAN cables, and
testing PICs, see the Port Interface Card Hardware Reference, which can be
downloaded from www.alliedtelesis.com/support/software.
PCI Accelerator Cards (PACs)
PCI Accelerator Cards (PACs) provide hardware data compression and
encryption on Rapier switches. A PAC is a hardware processing unit controlled
by the switch’s CPU. A PAC can be installed in the dedicated PAC slot on all
Rapier switches except the Rapier 48, Rapier 48i, Rapier 48w, Rapier 48w-B,
Rapier G6, and Rapier G6F.
Warning Only authorised service personnel should install a PAC. Opening the
switch’s lid may cause personal injury from electric shock, could damage the
switch, and will invalidate the product warranty.
Two PACs are available:
■ AT-AR060 EPAC, Encryption PAC
■ AT-AR061 ECPAC, Encryption/Compression PAC
How PACs work PACs have their own processor which operates independently of the base
system. This processor is responsible for the transfer of data between the base
system and the PAC, and the control of local high speed encryption and
compression data processing devices.
This architecture allows data encoding to be performed off-line without
involving the base switch processor, maximising PAC performance while
minimising the impact on the switch.
Compression PAC-based compression has the following features:
■ Local 32-bit processor for high speed control and data transfer.
■ Dedicated high performance 32-bit compression hardware.
■ High compression ratio Lempel-Ziv algorithm in hardware.
■ 2 MBytes of history memory.
■ Support for up to 127 compression channels.
Compression and decompression operations are performed by a 32-bit data
compression coprocessor specifically designed for high-performance Lempel-
Ziv compression applications. 2MBytes of history memory allows up to 127
separate data links to use compression concurrently, enabling PACs to provide
compression for complicated network architectures. Figure 22 on page 25
shows typical compression ratios achieved by a PAC for a representative set of
file types.
Encryption PAC-based encryption has the following features:
■ Local 32-bit processor for high speed control and data transfer.
■ Dedicated high performance 32-bit Data Encryption Standard – DES and
Triple DES (3DES) – hardware.