Datasheet

WRITE CYCLE 3 (LB#,UB# Controlled) (1,4,5)
Dout
Din
Data Valid
tDW tDH
(4)
High-Z
tWHZ
WE#
LB#,UB#
t
CW
CE#
Address
tWR
tAS
tAW
tWC
tWP
tBW
Notes :
1.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low.
2.During a WE#
controlled write cycle with OE# low, t
WP
must be greater than t
WHZ
+ t
DW
to allow the drivers to turn off and data to be placed
on the bus.
3.During this period, I/O pins are in the output state, and input signals must not be applied.
4.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.
5.t
OW
and t
WHZ
are specified with C
L
= 5pF. Transition is measured ±500mV from steady state.
AS7C34098B
Confidential
- 10 of 14 -
Rev.2.0. June 2017