Datasheet

®
AS7C34098A
Write waveform 3
10
Address
CE
LB, UB
WE
t
AS
t
WC
t
CW
t
AW
t
BW
t
WP
t
AH
t
WR
Data
IN
t
WZ
t
DW
Da t a valid
t
DH
Data
OUT
High Z
Data undefined
High Z
AC test conditions
- Output load: see Figure B.
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
+3.3V
+3.0V
GND
10%
2 ns
10%
D
OUT
350Ω C
GND
D
OUT
168Ω
Notes
Figure A: Input pulse Figure B: 3.3V Output load
1 During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A and B.
4 t
CLZ
and t
CHZ
are specified with C
L
= 5pF as in Figure B. Transition is measured ±500mV from steady-state voltage.
5 This parameter is guaranteed, but not tested.
6 WE is High for read cycle.
7 CE and OE are Low for read cycle.
8 Address valid prior to or coincident with CE transition Low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 All write cycle timings are referenced from the last valid address to the first transitioning address.
11 C=30pF, except on High Z and Low Z parameters, where C=5pF.
11/14/11,v. 2.2 Alliance Memory Inc P. 7 of 11