Datasheet
®
32K X 8 BIT LOW POWER CMOS SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
V
CC
for Data Retention V
DR
CE# V≧
CC
- 0.2V 1.5 - 5.5 V
Data Retention Current I
DR
V
CC
= 2.0V
CE# V≧
CC
- 0.2V
- 0.5 20
µ
A
Chip Disable to Data
Retention Time
t
CDR
See Data Retention
Waveforms (below)
0 - - ns
Recovery Time t
R
t
RC
*
- - ns
t
RC
*
= Read Cycle Time
DATA RETENTION WAVEFORM
Vcc
CE#
VDR ≧1.5V
CE# V≧ cc-0.2V
Vcc(min.)
V
IH
tRtCDR
VIH
Vcc(min.)
February 2007
AS6C62256
Alliance Memory Inc.
Page 7 of 12
March 23,2016 v1.2