Datasheet
®
32K X 8 BIT LOW POWER CMOS SRAM
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
AS6C62256-55
PARAMETER SYM
MIN MAX.
UNIT
Read Cycle Time t
RC
55 - ns
Address Access Time t
AA
- 55 ns
Chip Enable Access Time t
ACE
- 55 ns
Output Enable Access Time t
OE
- 30 ns
Chip Enable to Output in Low-Z t
CLZ
* 10 - ns
Output Enable to Output in Low-Z t
OLZ
* 5 - ns
Chip Disable to Output in High-Z t
CHZ
* - 20 ns
Output Disable to Output in High-Z t
OHZ
* - 20 ns
Output Hold from Address Change t
OH
10 - ns
(2) WRITE CYCLE
AS6C62256-55
PARAMETER SYM
MIN. MAX.
UNIT
Write Cycle Time t
WC
55 - ns
Address Valid to End of Write t
AW
50 - ns
Chip Enable to End of Write t
CW
50 - ns
Address Set-up Time t
AS
0 - ns
Write Pulse Width t
WP
45 - ns
Write Recovery Time t
WR
0 - ns
Data to Write Time Overlap t
DW
25 - ns
Data Hold from End of Write Time t
DH
0 - ns
Output Active from End of Write t
OW
* 5 - ns
Write to Output in High-Z t
WHZ
* - 20 ns
*These parameters are guaranteed by device characterization, but not production tested.
February 2007
AS6C62256
26/MAR/13, v1.1
March 23,2016 v1.2
Alliance Memory Inc.
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