February 2007 AS6C62256 REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue February 2007 Rev. 1.1 Revision of Supply current ISB1 – page 3 Commercial temp 20 µA Industrial temp 30 µA March 26, 2013 Revision of Alliance Memory address March 26, 2013 Rev 1.2 Further Revision of Supply current - page 3 Commercial temp 15 µA Industrial temp 30 µA March 23, 2016 IdR (data-retention current) to be 20uA - page 7 March 23,2016 v1.2 Alliance Memory Inc.
February 2007 AS6C62256 ® 32K X 8 BIT LOW POWER CMOS SRAM FEATURES GENERAL DESCRIPTION Access time : 55ns Low power consumption: Operation current : 15mA (TYP.), VCC = 3.0V Standby current : 1µ A (TYP.), VCC = 3.0V Wide range power supply : 2.7 ~ 5.5V Fully Compatible with all Competitors 5V product Fully Compatible with all Competitors 3.3V product All inputs and outputs TTL compatible Fully static operation Tri-state output Data retention voltage :1.5V (MIN.
February 2007 AS6C62256 ® 32K X 8 BIT LOW POWER CMOS SRAM PIN CONFIGURATION 1 28 Vcc A12 2 27 WE# A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 A3 7 A2 8 A1 9 AS6C62256 A14 23 A11 22 OE# 21 A10 20 CE# 19 DQ7 18 DQ6 A0 10 DQ0 11 DQ1 12 17 DQ5 DQ2 13 16 DQ4 Vss 14 15 DQ3 OE# A11 A9 A8 A13 WE# Vcc A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AS6C62256 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 Vss DQ2 DQ1 DQ0 A0 A1 A2
February 2007 AS6C62256 ® 32K X 8 BIT LOW POWER CMOS SRAM DC ELECTRICAL CHARACTERISTICS SYMBOL TEST CONDITION PARAMETER Supply Voltage VCC *1 Input High Voltage VIH *2 Input Low Voltage VIL Input Leakage Current ILI VCC >= VIN >= VSS Output Leakage VCC >= VOUT >= VSS, ILO Current Output Disabled Output High Voltage VOH IOH = -1mA Output Low Voltage VOL IOL = 2mA ICC Average Operating Power supply Current ICC1 Standby Power Supply Current ISB ISB1 Cycle time = Min. CE# = VIL , II/O = 0mA MIN. 2.7 2.
February 2007 AS6C62256 ® 32K X 8 BIT LOW POWER CMOS SRAM AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER SYM Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH (2) WRITE CYCLE PARAMETER SYM Write Cycle Time Address Valid to End of Write Chip Enable to
February 2007 AS6C62256 ® 32K X 8 BIT LOW POWER CMOS SRAM TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE OE# tCLZ Dout High-Z tOLZ tOE tOH tOHZ tCHZ Data Valid High-Z Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low. 3.
February 2007 AS6C62256 ® 32K X 8 BIT LOW POWER CMOS SRAM WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW tAS tWP tWR WE# tWHZ Dout TOW High-Z (4) tDW Din (4) tDH Data Valid WRITE CYCLE 2 (CE# Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tCW tWP WE# tWHZ Dout (4) High-Z tDW Din tDH Data Valid Notes : 1.WE#, CE# must be high during all address transitions. 2.A write occurs during the overlap of a low CE#, low WE#. 3.
February 2007 AS6C62256 ® 32K X 8 BIT LOW POWER CMOS SRAM DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time SYMBOL TEST CONDITION VDR CE# ≧ VCC - 0.2V VCC = 2.0V IDR CE# ≧ VCC - 0.2V See Data Retention tCDR Waveforms (below) tR MIN. 1.5 TYP. - MAX. 5.5 UNIT V - 0.5 20 µA 0 - - ns tRC* - - ns DATA RETENTION WAVEFORM VDR ≧1.5V Vcc Vcc(min.) Vcc(min.) tCDR CE# March 23,2016 v1.
February 2007 AS6C62256 ® 32K X 8 BIT LOW POWER CMOS SRAM PACKAGE OUTLINE DIMENSION 28 pin 600 mil PDIP Package Outline Dimension SYM. A1 A2 B B1 c D E E1 e eB L S Q1 Θ March 23,2016 v1.2 UNIT INCH.(BASE) 0.010 (MIN) 0.150±0.005 0.020 (MAX) 0.055 (MAX) 0.012 (MAX) 1.430 (MAX) 0.6 (TYP) 0.52 (MAX) 0.100 (TYP) 0.625 (MAX) 0.180(MAX) 0.06 (MAX) 0.08(MAX) o 15 (MAX) MM(REF) 0.254 (MIN) 3.810±0.127 0.508(MAX) 1.397(MAX) 0.304 (MAX) 36.322 (MAX) 15.24 (TYP) 13.208 (MAX) 2.540(TYP) 15.87 (MAX) 4.
February 2007 AS6C62256 ® 32K X 8 BIT LOW POWER CMOS SRAM 28 pin 330 mil SOP Package Outline Dimension SYM. A A1 A2 b c D E E1 e L L1 S y Θ March 23,2016 v1.2 UNIT INCH(BASE) 0.120 (MAX) 0.002(MIN) 0.098±0.005 0.016 (TYP) 0.010 (TYP) 0.728 (MAX) 0.340 (MAX) 0.465±0.012 0.050 (TYP) 0.05 (MAX) 0.067±0.008 0.047 (MAX) 0.003(MAX) o o 0 ～10 MM(REF) 3.048 (MAX) 0.05(MIN) 2.489±0.127 0.406(TYP) 0.254(TYP) 18.491 (MAX) 8.636 (MAX) 11.811±0.305 1.270(TYP) 1.270 (MAX) 1.702 ±0.203 1.194 (MAX) 0.
February 2007 AS6C62256 ® 32K X 8 BIT LOW POWER CMOS SRAM 28 pin 8mm x 13.4mm sTSOP Package Outline Dimension SYM. A A1 A2 b c Db E e D L L1 y Θ UNIT INCH(BASE) MM(REF) 0.047 (MAX) 0.004±0.002 0.039±0.002 0.006 (TYP) 0.010 (TYP) 0.465±0.004 0.315±0.004 0.022 (TYP) 0.528±0.008 0.020±0.004 0.0315±0.004 0.08(MAX) o o 0 ～5 1.20 (MAX) 0.10±0.05 1.00±0.05 0.15(TYP) 0.254(TYP) 11.80±0.10 8.00±0.10 0.55(TYP) 13.40±0.20 0.50±0.10 0.80±0.10 0.003(MAX) o o 0 ～5 Note：E dimension is not including end flash.
February 2007 AS6C62256 ® 32K X 8 BIT LOW POWER CMOS SRAM ORDERING INFORMATION Ordering Codes Alliance Organization VCC range Operating Speed Temp ns Commercial ~ 0º C to 70º C 55 Commercial ~ 0º C to 70º C 55 Industrial ~ -40ºC to 85º C 55 Commercial ~ 0º C to 70º C 55 Industrial ~ -40ºC to 85º C 55 Package AS6C62256-55PCN 32k x 8 2.7-5.5V 28pin 600mil PDIP AS6C62256-55SCN 32k x 8 2.7-5.5V 28pin 330mil SOP AS6C62256-55SIN 32k x 8 2.7-5.5V 28pin 330mil SOP AS6C62256-55STCN 32k x 8 2.7-5.
February 2007 AS6C62256 Rev 1.2 ® ® Alliance Memory, Inc. Copyright © Alliance Memory 511 Taylor Way, Suite#1, San Carlos, CA 94070 Tel: +1 650-610-6800 Fax: +1 650-620-9211 All Rights Reserved Part Number: AS6C62256 Document Version: v. 1.2 www.alliancememory.com © Copyright 2003 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance.
