Datasheet

AUGUST 2009
AS6C4008
512K X 8 BIT LOW POWER CMOS SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
VCC for Data Retention
V
DR
CE# ≧ V
CC
- 0.2V
1.5
-
5.5
V
Data Retention Current
I
DR
V
CC
= 1.5V
CE# ≧ V
CC
- 0.2V
-LL
-
2
30
µ
A
-LLE/-LLI
-
2
30
µ
A
Chip Disable to Data
Retention Time
t
CDR
See Data Retention
Waveforms (below)
0 - -
ns
Recovery Time
t
R
t
RC
*
-
-
ns
t
RC
*
= Read Cycle Time
DATA RETENTION WAVEFORM
Vcc
CE
#
Vcc(min.)
t
CDR
V IH
V DR ≧ 1.5V
CE# ≧ Vcc-0.2V
Vcc(min.)
t
R
V IH
AUG09 v1.4 Alliance Memory Inc Page 7 of 14