Datasheet

AUGUST 2009
AS6C4008
512K X 8 BIT LOW POWER CMOS SRAM
W
RITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
tWC
Address
tAW
CE#
tAS
tCW
tWP tWR
WE#
Dout
t
WHZ
(4)
High-Z
T
OW
(4)
tDW tDH
Din Data Valid
WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)
tWC
Address
tAW
CE# tAS tWR
tWP
tCW
WE#
Dout
t
WHZ
(4)
High-Z
tDW tDH
Din Data Valid
Notes :
1. WE#, CE# must be high during all address transitions.
2. A write occurs during the overlap of a low CE#, low WE#.
3. During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be
placed on
the bus.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.
6. tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
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