Datasheet

AUGUST 2009
AS6C4008
512K X 8 BIT LOW POWER CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC
Address
tAA tOH
Dout Previous Data Valid Data Valid
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
tRC
Address
tAA
CE#
tACE
OE#
Dout
High-Z
tCLZ
tOLZ
tOE tOH
tOHZ
tCHZ
Data Valid
High-Z
Notes :
1. WE# is high for read cycle.
2. Device is continuously selected OE# = low, CE# = low.
3. Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter.
4.t
CLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any gi
ven temperature and voltage condition, t
CHZ
is less than t
CLZ
, t
OHZ
is less than t
OLZ.
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