Datasheet

ManualsBrandsAlliance Memory ManualsMemory ICsSRAM 4MB 55ns SOP

AUGUST 2009

AS6C4008

512K X 8 BIT LOW POWER CMOS SRAM

SYMBOL

DESCRIPTION

A0 - A18

Address Inputs

DQ0 – DQ7

Data Inputs/Outputs

CE#

Chip Enable Inputs

WE#

Write Enable Input

OE#

Output Enable Input

Power Supply

Ground

No Connection

CONTROL

CIRCUIT

FEATURES GENERAL DESCRIPTION

Access time : 55 ns

Low power consumption:

Operating current : 30 mA (TYP.)

Standby current : 4 µA (TYP.)

Single 2.7V ~ 5.5V power supply

All outputs TTL compatible

Fully static operation

Tri-state output

Data retention voltage :1.5V (MIN.)

All products ROHS Compliant

Package : 32-pin 450 mil SOP;32-pin 600 mil P-DIP

32-pin 8mm x 20mm TSOP-I

32-pin 8mm x 13.4mm STSOP

36-ball 6mm x 8mm TFBGA

32-pin 400 mil TSOP-II

The AS6C4008 is a 4,194,304-bit low power

CMOS static random access memory organized as

524,288 words by 8 bits. It is fabricated using very

high performance, high reliability CMOS technology.

Its standby current is stable within the range of

operating temperature.

The AS6C4008 is well designed for very low power

system applications, and particularly well suited for

battery back-up non-volatile memory application.

The AS6C400

8 op erates from a sing le p owe r

sup p ly of 2.7V~ 5.5Vand all inputs and outputs are

fully TTL compatible

PRODUCT FAMILY

Product

Family

Operating

Temperature

Vcc Range Speed

Power Dissipation

Standby(ISB1TYP.)

Operating(Icc,TYP.)

AS6C4008

-40 ~ +85

℃

2.7 ~ 5.5V

55ns

4µA(LL)

30mA

FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION**

Vcc

Vss

A0-A18

DECODER

512Kx8

MEMORY ARRAY

DQ0-DQ7

I/O DATA

CIRCUIT

COLUMN I/O

CE#

WE#

OE#

Page 1 of 14

AUG/09, v 1.4 Alliance Memory Inc

Summary of content (14 pages)

PAGE 1
AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM FEATURES GENERAL DESCRIPTION Access time : 55 ns Low power consumption: Operating current : 30 mA (TYP.) Standby current : 4 µA (TYP.) Single 2.7V ~ 5.5V power supply All outputs TTL compatible Fully static operation Tri-state output Data retention voltage :1.5V (MIN.) All products ROHS Compliant Package : 32-pin 450 mil SOP;32-pin 600 mil P-DIP 32-pin 8mm x 20mm TSOP-I 32-pin 8mm x 13.
PAGE 2
AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM PIN CONFIGURATION 1 32 Vcc A16 2 31 A15 A14 3 30 A17 A12 4 29 WE# A7 5 28 A13 27 A8 26 A9 AS6C4008 A18 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 22 CE# A0 12 21 DQ7 DQ0 13 20 DQ6 DQ1 14 19 DQ5 DQ2 15 18 DQ4 Vss 16 17 DQ3 25 A11 24 OE# 23 A10 A11 A9 A8 A13 WE# A17 A15 Vcc A18 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 AS6C4008
PAGE 3
AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM ABSOLUTE MAXIMUM RATINGS* PARAMETER Terminal Voltage with Respect to VSS SYMBOL VTERM RATING -0.5 to 6.5 UNIT V 0 to 70(C grade) Operating Temperature Co TA -40 to 85(I grade) Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 sec) TSTG PD IOUT Co -65 to 150 1 50 260 TSOLDER W mA Co *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
PAGE 4
AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX 6 8 UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS 0.2V to VCC - 0.2V 3ns 1.
PAGE 5
AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE OE# tCLZ Dout High-Z tOLZ tOE tOH tOHZ tCHZ Data Valid High-Z Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low. 3.
PAGE 6
AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW tAS tWP tWR WE# TOW tWHZ Dout High-Z (4) tDW Din (4) tDH Data Valid WRITE CYCLE 2 (CE# Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tWP tCW WE# tWHZ Dout (4) High-Z tDW Din tDH Data Valid Notes : 1.WE#, CE# must be high during all address transitions. 2.A write occurs during the overlap of a low CE#, low WE#. 3.
PAGE 7
AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time SYMBOL TEST CONDITION VDR CE# ≧ VCC - 0.2V VCC = 1.5V -LL IDR CE# ≧ VCC - 0.2V -LLE/-LLI See Data Retention tCDR Waveforms (below) tR MIN. 1.5 - TYP. 2 2 MAX. 5.5 30 30 UNIT V µA µA 0 - - ns tRC* - - ns DATA RETENTION WAVEFORM VDR ≧ 1.5V Vcc(min.) Vcc(min.
PAGE 8
AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM PACKAGE OUTLINE DIMENSION 32 pin 450 mil SOP Package Outline Dimension UNIT SYM. A A1 A2 b c D E E1 e L L1 S y Θ AUG09 v1.4 INCH.(BASE) MM(REF) 0.118 (MAX) 0.004(MIN) 0.111(MAX) 0.016(TYP) 0.008(TYP) 0.817(MAX) 0.445 ±0.005 0.555 ±0.012 0.050(TYP) 0.0347 ±0.008 0.055 ±0.008 0.026(MAX) 0.004(MAX) o o 0 -10 2.997 (MAX) 0.102(MIN) 2.82(MAX) 0.406(TYP) 0.203(TYP) 20.75(MAX) 11.303 ±0.127 14.097 ±0.305 1.270(TYP) 0.881 ±0.203 1.397 ±0.203 0.
PAGE 9
AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM 32 pin 8mm x 20mm TSOP-I Package Outline Dimension UNIT SYM. A A1 A2 b c D E e HD L L1 y Θ AUG09 v1.4 INCH(BASE) MM(REF) 0.047 (MAX) 0.004 ±0.002 0.039 ±0.002 0.008 + 0.002 - 0.001 0.005 (TYP) 0.724 ±0.004 0.315 ±0.004 0.020 (TYP) 0.787 ±0.008 0.0197 ±0.004 0.0315 ±0.004 0.003 (MAX) o o 0 ～5 1.20 (MAX) 0.10 ±0.05 1.00 ±0.05 0.20 + 0.05 -0.03 0.127 (TYP) 18.40 ±0.10 8.00 ±0.10 0.50 (TYP) 20.00 ±0.20 0.50 ±0.10 0.08 ±0.10 0.
PAGE 10
AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM 32 pin 8mm x 13.4mm STSOP Package Outline Dimension HD cL 12° (2x) 32 16 17 12° (2x) b E e 1 "A" Seating Plane D y 12° (2X) 16 17 0.254 c A2 A GAUGE PLANE A1 0 SEATING PLANE L 12° (2X) L1 "A" DETAIL VIEW 1 32 UNIT SYM. A A1 A2 b c D E e HD L L1 y Θ AUG09 v1.4 INCH(BASE) MM(REF) 0.049 (MAX) 0.005 ±0.002 0.039 ±0.002 0.008 ±0.01 0.005 (TYP) 0.465 ±0.004 0.315 ±0.004 0.020 (TYP) 0.528±0.008 0.0197 ±0.004 0.0315 ±0.004 0.
PAGE 11
AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM 36 ball 6mm × 8mm TFBGA Package Outline Dimension AUG09 v1.
PAGE 12
AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM 32-pin 400mil TSOP-Ⅱ Package Outline Dimension AUG/09, v 1.0.
PAGE 13
AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM 32 pin 600 mil P-DIP Package Outline Dimension UNIT SYM. A1 A2 B D E E1 e eB L S Q1 INCH(BASE) MM(REF) 0.015 (MIN) 0.155 ± 0.005 0.018 ± 0.005 1.650 ± 0.005 0.600 ± 0.010 0.545 ± 0.005 0.100 (TYP) 0.640 ± 0.020 0.130 ± 0.010 0.075 ± 0.010 0.070 ± 0.005 0.381 (MIN) 3.937 ± 0.127 0.457 ± 0.127 41.910 ± 0.127 15.240 ± 0.254 13.843 ± 0.127 2.540 (TYP) 16.256 ± 0.508. 3.302 ± 0.254 1.905 ± 0.254 1.778 ± 0.
PAGE 14
AUGUST 2009 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM ORDERING INFORMATION Alliance Organization VCC Package AS6C4008-55PCN 512k x 8 5V 32pin 600mil DIP AS6C4008-55SIN 512k x 8 5V 32pin 450mil SOP AS6C4008-55TIN 512k x 8 5V 32pin TSOP 1 (8 x 20 mm) AS6C4008-55STIN 512k x 8 5V 32pin sTSOP (8 x 13.