Datasheet

WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
Dout
Din
Data Valid
tDW tDH
(4)
High-Z
tWHZ
WE#
tWP
tCW
tWRtAS
(4)
TOW
CE#
tAW
Address
tWC
CE2
WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6)
Dout
Din
Data Valid
tDW tDH
(4)
High-Z
tWHZ
WE#
tWP
tCW
CE# tWRtAS
tAW
Address
tWC
CE2
Notes :
1.WE#, CE# must be high or CE2 must be low during all address transitions.
2.A write occurs during the overlap of a low CE#, high CE2, low WE#.
3.During a WE#controlled write cycle with OE# low, t
WP
must be greater than t
WHZ
+ t
DW
to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high
impedance state.
6.t
OW
and t
WHZ
are specified with C
L
= 5pF. Transition is measured ±500mV from steady state.
®
February 2007
128K X 8 BIT LOW POWER CMOS SRAM
AS6C1008
02/February/07, v 1.0
Alliance Memory Inc.
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