Datasheet

®
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
Dout Data Valid
tOHtAA
Address
tRC
Previous Data Valid
READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5)
Dout Data Valid
tOH
OE#
High-ZHigh-Z
tCLZ
tOLZ
tOE
tCHZ
tOHZ
CE2
t
ACE
CE#
tAA
Address
tRC
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low
.,
CE2 = high
.
3.Address must be valid prior to or coincident with CE# = low
,
CE2 = high; otherwise t
AA
is the limiting parameter.
4.t
CLZ
, t
OLZ
, t
CHZ
and t
OHZ
are specified with C
L
= 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, t
CHZ
is less than t
CLZ
, t
OHZ
is less than t
OLZ.
February 2007
128K X 8 BIT LOW POWER CMOS SRAM
AS6C1008
02/February/07, v 1.0
Alliance Memory Inc.
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