Datasheet

ManualsBrandsAlliance Memory ManualsMemory ICsSRAM 1MB 55ns SOP

FEATURES

Access time :55ns

Low powe r consumption:

Operating current:10 mA (TYP.)

Standby c

urrent: 1 µA (TYP.)

Fully Compatible with all Competitors 3.3V product

Fully static operation

Tri-state output

Data retention voltage : 1.5V (MIN.)

All products are ROHS Compliant

Package : 32-pin 450 mil SOP

32-pin 600 mil P-DIP

32-pin 8mm

x 20mm TSOP-I

32-pin 8mm

x 13.4mm sTSOP

36-

ball 6mm x 8mm TFBGA

GENERA L DESCRIPTION

The AS6C1008 is a 1,048,57 6-bit low powe r

CMOS static random access memory organized as

131,072 words by 8 bits. It is

fabricated using very

high performance, high reliability

CMO S technolo gy. Its

standby current is stable within the ra nge of

operating te

mperature.

The AS6C1008 is well designed for ver

y low power

system applications, and particularly well suited for

battery

back-up non-volatile memory a pplication.

The AS6C1008 operates from a single power supply

of 2.7V ~ 5.5V.

FUNCTIONAL BLOCK DIAGRAM

DECODER

I/O DATA

CIRCUIT

CONTROL

CIRCUIT

128Kx8

MEMORY ARRAY

COLUMN I/O

A0-A16

Vcc

Vss

DQ0-DQ7

CE#

WE#

OE#

CE2

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0 - A16 Address Inputs

DQ0 – DQ7 Data Inputs/Outputs

CE#, CE2 Chip Enable Inputs

WE# Write Enable Input

OE# Output Enable Input

Power Supply

Ground

NC No C onnection

Single 2.7V ~ 5.5V powe r supply

Fully Compatible with all Competitors 5V product

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 1 of 14

Summary of content (14 pages)

PAGE 1
February 2007 AS6C1008 ® 128K X 8 BIT LOW POWER CMOS SRAM FEATURES GENERAL DESCRIPTION Access time :55ns Low powe r consumption: Operating current:10 mA (TYP.) Standby current: 1 µA (TYP.) Single 2.7V ~ 5.5V po we r supply Fully Compatible with all Competitors 5V product Fully Compatible with all Competitors 3.3V product Fully s tatic operation Tri-state output Data retention voltage : 1.5V (MIN.
PAGE 2
® February 2007 AS6C1008 128K X 8 BIT LOW POWER CMOS SRAM PIN CONFIGURATION Vcc 1 32 A16 2 31 A15 A14 3 30 CE2 A12 4 29 WE# A7 5 28 A13 A6 6 27 A8 A5 7 A4 8 A3 9 A2 10 A1 11 A0 AS6C1008 NC 26 A9 25 A11 24 OE# 23 A10 22 CE# 12 21 DQ7 DQ0 13 20 DQ6 DQ1 14 19 DQ5 DQ2 15 18 DQ4 Vss 16 17 DQ3 A1 1 A9 A8 A1 3 WE # CE 2 A1 5 Vc c NC A1 6 A1 4 A1 2 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AS6C1008 32 31 30 29 28 27 26 25 24 23 22 21 2
PAGE 3
February 2007 AS6C1008 ® 128K X 8 BIT LOW POWER CMOS SRAM ABSOLUTE MAXIMUM RATINGS* PARAMETER Terminal Voltage with Respect to VSS SYMBOL VTERM Operating Temperature RATING -0.5 to 7.0 0 to 70(C grade) UNIT V TA Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 sec) ºC -40 to 85(I grade) -65 to 150 1 50 260 TSTG PD IOUT TSOLDER ºC W mA ºC *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
PAGE 4
February 2007 AS6C1008 ® 128K X 8 BIT LOW POWER CMOS SRAM Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at V CC = VCC(TYP.) and TA = 25ºC CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN.
PAGE 5
February 2007 AS6C1008 ® 128K X 8 BIT LOW POWER CMOS SRAM TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE CE2 OE# tCLZ Dout High-Z tOLZ tOE tOH tOHZ tCHZ Data Valid High-Z Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low., CE2 = high. 3.
PAGE 6
February 2007 AS6C1008 ® 128K X 8 BIT LOW POWER CMOS SRAM WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW CE2 tAS tWP tWR WE# tWHZ Dout TOW High-Z (4) tDW (4) tDH Data Valid Din WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tCW CE2 tWP WE# tWHZ Dout (4) High-Z tDW Din tDH Data Valid Notes : 1.WE#, CE# must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE#, high CE2, low WE#. 3.
PAGE 7
February 2007 AS6C1008 ® 128K X 8 BIT LOW POWER CMOS SRAM DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL VCC for Data Retention VDR Data Retention Current IDR TEST CONDITION CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V VCC = 1.5V CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V C** MIN. TYP. MAX. UNIT 1.5 - 5.5 V - 0.
PAGE 8
February 2007 AS6C1008 ® 128K X 8 BIT LOW POWER CMOS SRAM PACKAGE OUTLINE DIMENSION 32 pin 450 mil SOP Package Outline Dimension SYM. A A1 A2 b c D E E1 e L L1 S y Θ 02/February/07, v 1.0 UNIT INCH.(BASE) MM(REF) 0.118 (MAX) 0.004(MIN) 0.111(MAX) 0.016(TYP) 0.008(TYP) 0.817(MAX) 0.445 ±0.005 0.555 ±0.012 0.050(TYP) 0.0347 ±0.008 0.055 ±0.008 0.026(MAX) 0.004(MAX) o o 0 -10 2.997 (MAX) 0.102(MIN) 2.82(MAX) 0.406(TYP) 0.203(TYP) 20.75(MAX) 11.303 ±0.127 14.097 ±0.305 1.270(TYP) 0.881 ±0.203 1.
PAGE 9
February 2007 AS6C1008 ® 128K X 8 BIT LOW POWER CMOS SRAM 32 pin 600 mil P-DIP Package Outline Dimension SYM. A1 A2 B D E E1 e eB L S Q1 UNIT INCH(BASE) MM(REF) 0.001 (MIN) 0.150 ± 0.005 0.018 ± 0.005 1.650 ± 0.005 0.600 ± 0.010 0.544 ± 0.004 0.100 (TYP) 0.640 ± 0.020 0.130 ± 0.010 0.075 ± 0.010 0.070 ± 0.005 0.254 (MIN) 3.810 ± 0.127 0.457 ± 0.127 41.910 ± 0.127 15.240 ± 0.254 13.818 ± 0.102 2.540 (TYP) 16.256 ± 0.508. 3.302 ± 0.254 1.905 ± 0.254 1.778 ± 0.
PAGE 10
February 2007 AS6C1008 ® 128K X 8 BIT LOW POWER CMOS SRAM 32 pin 8mm x 20mm TSOP-I Package Outline Dimension UNIT SYM. A A1 A2 b c D E e HD L L1 y Θ 02/February/07, v 1.0 INCH(BASE) MM(REF) 0.047 (MAX) 0.004 ±0.002 0.039 ±0.002 0.008 + 0.002 - 0.001 0.005 (TYP) 0.724 ±0.004 0.315 ±0.004 0.020 (TYP) 0.787 ±0.008 0.0197 ±0.004 0.0315 ±0.004 0.003 (MAX) o o 0 ～5 1.20 (MAX) 0.10 ±0.05 1.00 ±0.05 0.20 + 0.05 -0.03 0.127 (TYP) 18.40 ±0.10 8.00 ±0.10 0.50 (TYP) 20.00 ±0.20 0.50 ±0.10 0.08 ±0.10 0.
PAGE 11
February 2007 AS6C1008 ® 128K X 8 BIT LOW POWER CMOS SRAM 32 pin 8mm x 13.4mm sTSOP Package Outline Dimension HD cL 12° (2x) 32 16 17 12° (2x) b E e 1 "A" Seating Plane D y 12° (2X) 16 17 0.254 A2 c A GAUGE PLANE A1 0 SEATING PLANE "A" DETAIL VIEW 1 L1 32 SYM. UNIT A A1 A2 b c D E e HD L L1 y Θ 02/February/07, v 1.0 L 12° (2X) INCH(BASE) MM(REF) 0.049 (MAX) 0.005 ±0.002 0.039 ±0.002 0.008 ±0.01 0.005 (TYP) 0.465 ±0.004 0.315 ±0.004 0.020 (TYP) 0.528±0.008 0.0197 ±0.004 0.
PAGE 12
February 2007 AS6C1008 128K X 8 BIT LOW POWER CMOS SRAM 36 ball 6mm × 8mm TFBGA Package Outline Dimension 02/February/07, v 1.0 Alliance Memory Inc.
PAGE 13
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February 2007 AS6C1008 128K X 8 BIT LOW POWER CMOS SRAM ® ® Alliance Memory, Inc. 1116 South Amphlett, #2, San Mateo, CA 94402 Tel: 650-525-3737 Fax: 650-525-0449 Copyright © Alliance Memory All Rights Reserved Part Number: AS6C1008 Document Version: v. 1.0 www.alliancememory.com © Copyright 2003 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance.