Datasheet

AS4C8M16SA
Confidential 20 Rev. 2.2 Mar /2014
Table 17. LVTTL Interface
Reference Level of Output Signals
1.4V / 1.4V
Output Load
Reference to the Under Output Load (B)
Input Signal Levels
2.4V / 0.4V
Transition Time (Rise and Fall) of Input Signals
1ns
Reference Level of Input Signals
1.4V
3.3V
1.2k
870
30pF
Output
1.4V
50 
Output
30pF
50 
Z0=
Figure 18.1 LVTTL D.C. Test Load (A) Figure 18.2 LVTTL A.C. Test Load (B)
7. Transition times are measured between V
IH
and V
IL
. Transition (rise and fall) of input signals are in a fixed
slope (1 ns).
8. t
HZ
defines the time in which the outputs achieve the open circuit condition and are not at reference levels.
9. If clock rising time is longer than 1 ns, (t
R
/ 2 -0.5) ns should be added to the parameter.
10. Assumed input rise and fall time t
T
(t
R
& t
F
) = 1 ns
If t
R
or t
F
is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns should
be added to the parameter.
11. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to V
DD
and V
DDQ
(simultaneously) when CKE= “L”, DQM= “H” and all input signals
are held "NOP" state.
2) Start clock and maintain stable condition for minimum 200 s, then bring CKE= “H” and, it is
recommended that DQM is held "HIGH" (V
DD
levels) to ensure DQ output is in high impedance.
3) All banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the
device.
* The Auto Refresh command can be issue before or after Mode Register Set command