Datasheet

Figure 31. Write burst interrupt timing: (CL=3, AL=0, RL=3, WL=2, BL=8)

CK#

CMD

NOP Write A NOP Write B NOP NOP NOP NOP NOP NOP

A1 A2 A3

B1 B2 B3

B5 B6 B7

DQS

DQS#

DQs

NOTE 1: Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.

NOTE 2: Write burst of 8 can only be interrupted by another Write command. Write burst interruption by Read command or

Precharge command is prohibited.

NOTE 3: Write burst interrupt must occur exactly two clocks after previous Write command. Any other Write burst interrupt

timings are prohibited.

NOTE 4: Write burst interruption is allowed to any bank inside DRAM.

NOTE 5: Write burst with Auto Precharge enabled is not allowed to interrupt.

NOTE 6: Write burst interruption is allowed by another Write with Auto Precharge command.

NOTE 7: All command timings are referenced to burst length set in the mode register. They are not referenced to actual

burst. For example, minimum Write to Precharge timing is WL + BL/2 + tWR where tWR starts with the rising clock after the

uninterrupted burst end and not from the end of actual burst end.

AS4C64M16D2A-25BIN

AS4C64M16D2A-25BCN

Confidential

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Rev.1.1 October 2017