Datasheet

Figure 25. Read burst interrupt timing: (CL=3, AL=0, RL=3, BL=8)
CK#
CK
CMD
Read A
NOP
Read B
NOP NOP NOP NOP NOP NOP NOP
A0
A1 A2 A3
B0
B1 B2 B3
B4
B5 B6 B7
DQS
DQS#
DQs
NOTE 1: Read burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.
NOTE 2: Read burst of 8 can only be interrupted by another Read command. Read burst interruption by Write
command or Precharge command is prohibited.
NOTE 3: Read burst interrupt must occur exactly two clocks after previous Read command. Any other Read burst
interrupt timings are prohibited.
NOTE 4: Read burst interruption is allowed to any bank inside DRAM.
NOTE 5: Read burst with Auto Precharge enabled is not allowed to interrupt.
NOTE 6: Read burst interruption is allowed by another Read with Auto Precharge command.
NOTE 7: All command timings are referenced to burst length set in the mode register. They are not referenced to
actual burst. For example, Minimum Read to Precharge timing is AL+BL/2 where BL is the burst length set in the
mode register and not the actual burst (which is shorter because of interrupt).
Figure 26. Data input (write) timing
DQS#
DQ
DQS
t
DQSH
t
WPRE
DQS
DM
t
DQSL
t
WPSL
V
IL(ac)
V
IH(ac)
D
D
V
IL(dc)
V
IH(dc)
D
D
DMin DMin
DQS#
DMin
V
IH(ac)
V
IL(ac)
DMin
V
IH(dc)
V
IL(dc)
t
DS
t
DS
t
DH
t
DH
AS4C64M16D2A-25BIN
AS4C64M16D2A-25BCN
Confidential
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Rev.1.1 October 2017