Datasheet

Figure 16. ODT timing mode switch at exit power-down mode
CK#
CK
t
IS
CKE
t
AOFD
t
AOND
ODT
t
AXPD
T0 T1 T4 T5 T6 T7 T8 T9 T10 T11
Exiting from Slow Active Power Down Mode or Precharge power Down Mode.
Internal
Term Res.
t
IS
V
IL(ac)
ODT
Internal
Term Res.
t
IS
V
IL(ac)
Active & Standby mode
timings to be applied.
Power Down mode
timings to be applied.
t
IS
V
IH(ac)
Active & Standby mode
timings to be applied.
t
AONPD max
t
IS
V
IH(ac)
Power Down mode
timings to be applied.
ODT
ODT
Internal
Term Res.
Internal
Term Res.
RTT
t
AOFPD max
V
IH(ac)
RTT
RTT
RTT
Figure 17. Bank activate command cycle (t
RCD
=3, AL=2, t
RP
=3, t
RRD
=2, t
CCD
=2)
CK#
T0 T1
T2
T3 Tn Tn+1 Tn+2
Internal RAS# - CAS# delay (>=t
RCD min
)
CAS# - CAS# delay time (t
CCD
)
t
RCD
= 1
Read Begins
Tn+3
Bank A
Row Addr.
Bank A
Col. Addr.
Bank B
Row Addr.
Bank B
Col. Addr
Bank A
Addr.
Bank B
Addr.
Bank A
Row Addr.
Additive latency delay (AL)
Bank A
Activate
Bank A
Post CAS#
Read
Bank B
Activate
Bank B
Post CAS#
Read
Bank A
Precharge
Bank B
Precharge
Bank A
Activate
RAS# - RAS# delay time (>=t
RRD
)
Bank Active (>=t
RAS
)
Bank precharge time (>=t
RP
)
RAS# Cycle time (>=t
RC
)
ADDRESS
COMMAND
CK
AS4C64M16D2A-25BIN
AS4C64M16D2A-25BCN
Confidential
- 40 of 62 -
Rev.1.1 October 2017