Datasheet

Figure 10. OCD adjust mode
CK#
WL
CK
DQS_in
DQ_in
DQS#
t
DS
t
DH
CMD
OCD calibration mode exit
WR
OCD adjust mode
EMRS NOP NOP NOP NOP NOP
EMRS
NOP
DT0 DT1 DT3DT2
V
IH(ac)
V
IL(ac)
V
IH(dc)
V
IL(dc)
DM
NOTE 1: For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1t
CK
and t
DS
/t
DH
should be met as shown in the figure.
NOTE 2: For input data pattern for adjustment, DT0-DT3 is a fixed order and is not affected by burst type
(i.e., sequential or interleave)
Figure 11. ODT update delay timing-tMOD
CK
Updating
Rtt
t
IS
EMRS NOP
NOP
NOP
NOP
NOP
CMD
t
AOFD
t
MOD, max
t
MOD, min
Old setting New setting
ODT
NOTE 1: To prevent any impedance glitch on the channel, the following conditions must be met:
-t
AOFD
must be met before issuing the EMRS command.
- ODT must remain LOW for the entire duration of t
MOD
window, until t
MOD
, max is met.
then the ODT is ready for normal operation with the new setting, and the ODT signal may be raised again to turned
on the ODT.
NOTE 2: EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal).
NOTE 3: "setting" in this diagram is the Register and I/O setting, not what is measured from outside.
CK#
AS4C64M16D2A-25BIN
AS4C64M16D2A-25BCN
Confidential
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Rev.1.1 October 2017