Datasheet

NOTE 38: When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t
ERR
(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.)
NOTE 39: When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tJIT(per) of the input clock. (output deratings are relative to the SDRAM input clock.)
NOTE 40: When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t
JIT
(duty) of the input clock. (output deratings are relative to the SDRAM input clock.)
NOTE 41: When the device is operated with input clock jitter, this parameter needs to be derated by { -
t
JIT
(duty),max - t
ERR
(6-10per),max } and { - t
JIT
(duty),min - t
ERR
(6-10per),min } of the actual input clock.
(output deratings are relative to the SDRAM input clock.)
NOTE 42: For t
AOFD
of DDR2-800, the 1/2 clock of t
CK
in the 2.5 x t
CK
assumes a t
CH
(avg), average input 
 pulse width of 0.5 relative to t
CK
(avg). t
AOF
,min and t
AOF
,max should each be derated by the
same amount as the actual amount of t
CH
(avg) offset present at the DRAM input with respect to 0.5.
NOTE 43: If refresh timing is violated, data corruption may occur and the data must be re-writtern with valid data
before a valid READ can be executed.
NOTE 44: This is an optional feature. For detailed information, please refer to “operating temperature condition”.
AS4C64M16D2A-25BIN
AS4C64M16D2A-25BCN
Confidential
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Rev.1.1 October 2017