Datasheet

NOTE 17: ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is
when the bus is in high impedance. Both are measured from t
AOFD
, which is interpreted differently per
speed bin. For DDR2-, if t
CK
(avg) = 3 ns is assumed, t
AOFD
is 1.5 ns (= 0.5 x 3 ns) after the second
trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the
actual input clock edges.
NOTE 18: t
HZ
and t
LZ
transitions occur in the same access time as valid data transitions. These parameters are
referenced to a specific voltage level which specifies when the device output is no longer driving (t
HZ
), or
begins driving (t
LZ
).
NOTE 19: t
RPST
end point and t
RPRE
begin point are not referenced to a specific voltage level but specify when the
device output is no longer driving (t
RPST
), or begins driving (t
RPRE
). The actual voltage measurement
points are not critical as long as the calculation is consistent.
NOTE 20: Input waveform timing t
DS
with differential data strobe enabled MR[bit10]=0, is referenced from the input
signal crossing at the V
IH
(ac) level to the differential data strobe crosspoint for a rising signal, and from
the input signal crossing at the V
IL
(ac) level to the differential data strobe crosspoint for a falling signal
applied to the device under test. DQS, DQS# signals must be monotonic between V
IL
(dc)max and
V
IH
(dc)min.
NOTE 21: Input waveform timing t
DH
with differential data strobe enabled MR[bit10]=0, is referenced from the
differential data strobe crosspoint to the input signal crossing at the V
IH
(dc) level for a falling signal and
from the differential data strobe crosspoint to the input signal crossing at the V
IL
(dc) level for a rising
signal applied to the device under test. DQS, DQS# signals must be monotonic between V
IL
(dc)max and
V
IH
(dc)min.
NOTE 22: Input waveform timing is referenced from the input signal crossing at the V
IH
(ac) level for a rising signal
and V
IL
(ac) for a falling signal applied to the device under test.
NOTE 23: Input waveform timing is referenced from the input signal crossing at the V
IL
(dc) level for a rising signal
and V
IH
(dc) for a falling signal applied to the device under test.
NOTE 24: t
WTR
is at lease two clocks (2 x t
CK
) independent of operation frequency.
NOTE 25: t
CKE
min of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must
remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after
any CKE transition, CKE may not transition from its valid level during the time period of t
IS
+ 2 x t
CK
+ t
IH
.
NOTE 26: If t
DS
or t
DH
is violated, data corruption may occur and the data must be re-written with valid data before a
valid READ can be executed.
NOTE 27: These parameters are measured from a command/address signal (CKE, CS#, RAS#, CAS#, WE#, ODT,
BA0, A0, A1, etc.) transition edge to its respective clock signal (CK/CK#) crossing. The spec values are
not affected by the amount of clock jitter applied (i.e. t
JIT
(per), t
JIT
(cc), etc.), as the setup and hold are
relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
NOTE 28: These parameters are measured from a data strobe signal (LDQS/UDQS) crossing to its respective
clock signal (CK/CK#) crossing. The spec values are not affected by the amount of clock jitter applied
(i.e. t
JIT
(per), t
JIT
(cc), etc.), as these are relative to the clock signal crossing. That is, these parameters
should be met whether clock jitter is present or not.
NOTE 29: These parameters are measured from a data signal ((L/U) DM, (L/U) DQ0, (L/U) DQ1, etc.) transition
edge to its respective data strobe signal (LDQS/UDQS/LDQS#/UDQS#) crossing.
NOTE 30: For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM =
RU{tPARAM / t
CK
(avg)}, which is in clock cycles, assuming all input clock jitter specifications are satisfied.
NOTE 31: t
DAL
[t
CK
] = WR [t
CK
] + tRP [t
CK
] = WR + RU {t
RP
[ps] / t
CK
(avg) [ps] }, where WR is the value programmed
in the mode register set.
NOTE 32: New units, „t
CK
(avg)‟ is introduced in DDR2-800. Unit „t
CK
(avg)‟ represents  
t
CK
(avg) of the input clock under operation.
NOTE 33: Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as
'input clock jitter spec parameters' and these parameters apply to DDR2- only. The jitter specified
is a random jitter meeting a Gaussian distribution.
AS4C64M16D2A-25BIN
AS4C64M16D2A-25BCN
Confidential
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Rev.1.1 October 2017