Datasheet

Basic Functionality
The DDR4 SDRAM is a high-speed dynamic random-access memory internally organized with sixteen-
banks (4 bank groups each with 4 banks). The DDR4 SDRAM uses a 8n prefetch architecture to achieve high-
speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM consists of a
single 8n-bit wide, four clock data transfer at the internal DRAM core and eight corresponding n-bit wide, one-
half clock cycle data transfers at the I/O pins.
Read and write operation to the DDR4 SDRAM are burst oriented, start at a selected location, and continue
for a burst length of eight or a ‘chopped’ burst of four in a programmed sequence. Operation begins with the
registration of an Activate Command, which is then followed by a Read or Write command. The address bits
registered coincident with the Activate Command are used to select the bank and row to be activated (BG0
select the bank group; BA0-BA1 select the bank; A0-A14 select the row). The address bits registered
coincident with the Read or Write command are used to select the starting column location for the burst
operation, determine if the auto precharge command is to be issued (via A10), and select BC4 or BL8 mode
‘on the fly’ (via A12) if enabled in the mode register.
Prior to normal operation, the DDR4 SDRAM must be powered up and initialized in a predefined manner.
The following sections provide detailed information covering device reset and initialization, register definition,
command descriptions, and device operation.
Reset and Initialization Procedure
For power-up and reset initialization, in order to prevent DRAM from functioning improperly, default values
for the following MR settings need to be defined:
Gear down mode (MR3 A[3]) : 0 = 1/2 Rate
Per DRAM Addressability (MR3 A[4]) : 0 = Disable
Max Power Saving Mode (MR4 A[1]) : 0 = Disable
CS# to Command/Address Latency (MR4 A[8:6]) : 000 = Disable
CA Parity Latency Mode (MR5 A[2:0]) : 000 = Disable
Hard Post Package Repair mode (MR4 A[13]) : 0 = Disable
Soft Post Package Repair mode (MR4 A[5]) : 0 = Disable
Power-up Initialization Sequence
The following sequence is required for Power up and Initialization:
1. Apply power (Reset# is recommended to be maintained below 0.2 x V
DD
; all other inputs may be undefined).
Reset# needs to be maintained below 0.2 x V
DD
for minimum 200us with stable power need to be maintained
below 0.2 x V
DD
for minimum 700us with stable power. CKE is pulled “Low” anytime before Reset# being
de-asserted (min. time 10ns). The power voltage ramp time between 300mV to V
DD,min
must be no greater
than 200ms; and during the ramp, V
DD
≥ V
DDQ
and (V
DD
-V
DDQ
) < 0.3 V. V
PP
must ramp at the same time or
earlier than V
DD
and V
PP
must be equal to or higher than V
DD
at all times.
During power-up, either of the following conditions may exist and must be met:
Condition A:
 V
DD
and V
DDQ
are driven from a single power converter output, AND
 The voltage levels on all pins other than V
DD
, V
DDQ
, V
SS
, V
SSQ
must be less than or equal to V
DDQ
and V
DD
on one side and must be larger than or equal to V
SSQ
and V
SS
on the other side. In addition, V
TT
is limited
to 0.76 V max once power ramp is finished, AND
 V
REFCA
tracks V
DD
/2.
Condition B:
 Apply V
DD
without any slope reversal before or at the same time as V
DDQ
 Apply V
DDQ
without any slope reversal before or at the same time as V
TT
& V
REFCA
.
 Apply V
PP
without any slope reversal before or at the same time as V
DD
.
 The voltage levels on all pins other than V
DD
, V
DDQ
, V
SS
, V
SSQ
must be less than or equal to V
DDQ
and V
DD
on one side and must be larger than or equal to V
SSQ
and V
SS
on the other side.
2. After Reset# is de-asserted, wait for another 500us until CKE becomes active. During this time, the DRAM
will start internal initialization; this will be done independently of external clocks.
AS4C512M8D4
Confidential
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Rev.1.0. Aug.2019