Datasheet

CKE transition during the mode
CKE toggle is allowed when DRAM is in the maximum power saving mode. To prevent the device from
exiting the mode, CS# should be issued ‘High’ at CKE ‘L’ to ’H’ edge with appropriate setup tMPX_S and hold
tMPX_HH timings.
Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 Tb3 Tc0 Tc1 Tc2
Td0 Td1
CK#
CK
Td2 Td3 Td4
DON'T CARE
Td5
CKE
Td6 Td7
RESET#
CMD
CS#
t
MPX_S
t
MPX_HH
Figure 41. CKE Transition Limitation to hold Maximum Power Saving Mode
Maximum Power-Saving Mode Exit
signal level is detected ‘L’, then the DRAM initiates internal exit procedure from the power saving mode. CK
must be restarted and stable tCKMPX period before the device can exit the maximum power saving mode.
During the exit time tXMP, any valid commands except DES command is not allowed to DDR4 SDRAM and
also tXMP_DLL, any valid commands requiring a locked DLL is not allowed to DDR4 SDRAM.
When recovering from this mode, the DRAM clears the MRS bits of this mode. It means that the setting of
MR4 A1 is move to ’0’ automatically.
DRAM monitors CS# signal level and when it detects CKE ‘L’ to ’H’ transition, and either exits from the
power saving mode or stay in the mode depending on the CS# signal level at the CKE transition. Because CK
receivers are shut down during this mode, CS# = ’L’ is captured by rising edge of the CKE signal. If CS# signal
level is detected ‘L’, then the DRAM initiates internal exit procedure from the power saving mode. CK must be
restarted and stable tCKMPX period before the device can exit the maximum power saving mode. During the
exit time tXMP, any valid commands except DES command is not allowed to DDR4 SDRAM and also tXMP_DLL,
any valid commands requiring a locked DLL is not allowed to DDR4 SDRAM.
When recovering from this mode, the DRAM clears the MRS bits of this mode. It means that the setting of
MR4 [A1] is move to ’0’ automatically.
NOP NOP NOP NOP NOP DES
DES
Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 Tb3 Tc0 Tc1 Tc2
Tc3 Tc4
CK#
CK
Td0 Td1 Td2
DES DES DES
DON'T CARE
Td3
CKE
Te0 Te1
t
CKMPX
t
XMP
t
MPX_LH
RESET#
CMD
CS#
t
MPX_S
VALID DES VALID
t
XMP_DLL
Figure 42. Maximum Power Saving Mode Exit Sequence
AS4C512M8D4
Confidential
- 56 of 196 -
Rev.1.0. Aug.2019