Datasheet

Maximum Power Saving Mode
This mode provides lowest power consuming mode which could be similar to the Self-Refresh status with
no internal refresh activity. When DDR4 SDRAM is in the maximum power saving mode, it does not need to
guarantee data retention nor respond to any external command (except maximum power saving mode exit
and asserting RESET# signal LOW) to minimize the power consumption.
Maximum Power-Saving Mode Entry
Max power saving mode is entered through an MRS command. For devices with shared control/address
signals, a single DRAM device can be entered into the max power saving mode using the per DRAM
Addressability MRS command. Note that large CS# hold time to CKE upon the mode exit may cause DRAM
malfunction, thus it is required that the CA parity, CAL are disabled prior to the max power saving mode entry
MRS command.
When entering Maximum Power Saving mode, only DES commands are allowed until t
MPED
is satisfied. After
t
MPED
period from the mode entry command, DRAM is not responsive to any input signals except CS#, CKE
and RESET# signals, and all other input signals can be High-Z. CLK should be valid for t
CKMPE
period and then
can be High-Z.
MRSDES DES DES DES
Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 Tb3 Tc0 Tc1 Tc2
Tc3 Tc4
CK#
CK
Tc5 Tc6 Tc7
DON'T CARE
Tc8
CKE
Tc9 Tc10
RESET#
t
CKMPE
MR4[A1=1]
(MPSM Enable)
t
MPED
CMD
CS#
Figure 39. Maximum Power Saving mode Entry
The sequence and timing required for the maximum power-saving mode with the per-DRAM addressability
enabled is illustrated in the figure below.
MRSDES DES DES DES DES DES DES DES DES DES
DES
Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6
Tb7 Tb8
CK#
CK
Tb9 Tc0 Tc1
DES DES DES
DON'T CARE
Td0
CKE
Td1 Td2
t
PDA_S
t
MPED
t
CKMPE
AL + CWL
RESET#
CMD
CS#
MR4[A1=1]
(MPSM Enable)
t
PDA_H
DQ
DQS, DQS#
Figure 40. Maximum Power Saving mode Entry with PDA
AS4C512M8D4
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Rev.1.0. Aug.2019