Datasheet

Soft Post Package Repair (sPPR)
Soft Post Package Repair (sPPR) is a way to quickly, but temporarily, Repair a row element in a Bank Group
on a DDR4 DRAM device, contrasted to hard Post Package Repair which takes longer but is permanent repair
of a row element. There are some limitations and differences between sPPR and hPPR.
Table 55. Description and Comparison of hPPR and sPPR
Topic
Soft Repair
Hard Repair
Note
Persistence of Repair
Volatile – repair persists while
power is within operating range
Non-Volatile – repair is
permanent after the repair cycle
sPPR cleared after power off or device
reset
t
PGM
(hPPR and sPPR
programming Time)
WL+ 4t
CK
+t
WR
>2000ms(tPGM)
# of Repair elements
1 per BG
1 per BG
Once hPPR is used within a BG, sPPR is
no longer supported in that BG
Simultaneous use of soft
and hard repair within a BG
Previous hPPR are allowed
before soft repair to a different
BG
Any outstanding sPPR
must be cleared before a
hard repair
Clearing sPPR occurs by either:
(a) power down and power-up sequence
or
(b) Reset and re-initialize.
Repair Sequence
1 method – WR cmd.
2 methods WRA
and WR
Bank
(1)
not having row
repair retains array data
Yes
Yes, if WRA sequence;
No, if WR sequence
WRA sequence requires use of REF
commands
Bank
(1)
having row
repair retain array data
Yes, except for seed and
associated rows
No
sPPR must be performed outside of REF
window (t
RFC
)
Note 1. If a BA pin is defined to be an “sPPR associated row” to the seed row, both states of the BA address input are affected. For
example if BA0 is selected as an “sPPR associated row” to the seed row, addresses in both BA0 = 0 and BA0 = 1 are equally
affected.
sPPR mode is entered in a similar fashion as hPPR, sPPR uses MR4 bit A5 while hPPR uses MR4 bit A13;
sPPR requires the same guard key sequence as hPPR to qualify the MR4 PPR entry. Prior to sPPR entry,
either an hPPR exit command or an sPPR exit command should be performed, which ever was the last PPR
entry. After sPPR entry, an ACT command will capture the target bank and target row, herein seed row, where
the row repair will be made. After t
RCD
time, a WR command is used to select the individual DRAM, through
the DQ bits, to transfer the repair address into an internal register in the DRAM. After a write recovery time
and PRE command, the sPPR mode can be exited and normal operation can resume. The DRAM will retain
the sPPR change as long as V
DD
remains within the operating region. If the DRAM power is removed or the
DRAM is reset, all sPPR changes will revert to the unrepaired state. sPPR changes must be cleared by either
a power-up sequence or re-initialization by reset signal before hPPR mode is enabled.
DDR4 sPPR can repair one row per Bank Group, however when the hPPR resources for a bank group have
been used, sPPR resources are no longer available for that bank group. If an sPPR or hPPR repair sequence
is issued to a bank group with PPR resource un-available, the DRAM will ignore the programming sequence.
sPPR mode is optional for 4Gb density DDR4 device.
The bank receiving sPPR change is expected to retain array data in all other rows except for the seed row and
its associated row addresses. If the user does not require the data in the array in the bank under sPPR repair
to be retained, then the handling of the seed row’s associated row addresses is not of interest and can be
ignored. If the user requires the data in the array to be retained in the bank under sPPR mode, then prior to
executing the sPPR mode, the seed row and its associated row addresses should be backed up and restored
after sPPR has been completed. sPPR associated seed row addresses are specified in the table below.
Table 56. sPPR Associated Row Address
sPPR Associated Row Addresses
BA0
A16
A15
A14
A13
A1
A0
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Rev.1.0. Aug.2019