Datasheet

Table 6. CKE Truth Table
Current State
(2)
CKEn-1
(1)
CKEn
(1)
Command n
(3)
RAS#, CAS#, WE#, CS#
Action n
(3)
Notes
Power-Down
L
L
X
Maintain Power-Down
14,15
L
H
Deselect
Power-Down Exit
11,14
Self-Refresh
L
L
X
Maintain Self-Refresh
15,16
L
H
Deselect
Self-Refresh Exit
8,12,16
Bank(s) Active
H
L
Deselect
Active Power-Down Entry
11,13,14
Reading
H
L
Deselect
Power-Down Entry
11,13,14,17
Writing
H
L
Deselect
Power-Down Entry
11,13,14,17
Precharging
H
L
Deselect
Power-Down Entry
11,13,14,17
Refreshing
H
L
Deselect
Precharge Power-Down Entry
11
All Banks Idle
H
L
Deselect
Precharge Power-Down Entry
11,13,14,18
H
L
Refresh
Self-Refresh
9,13,18
See Command Truth Table for additional command details
10
Notes:
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2. Current state is defined as the state of the DDR4 SDRAM immediately prior to clock edge n.
3. Command n is the command registered at clock edge n, and Action n is a result of command n, ODT is not included here.
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
6. During any CKE transition (registration of CKE H → L or CKE L → H) the CKE level must be maintained until 1nCK prior to t
CKEmin
being
satisfied (at which time CKE may transition again).
7. Deselect and NOP are defined in the Command Truth Table.
8. On Self Refresh Exit Deselect commands must be issued on every clock edge occurring during the t
XS
period. Read or ODT commands
may be issued only after t
XSDLL
is satisfied.
9. Self Refresh mode can only be entered from the All Banks Idle state.
10. Must be a legal command as defined in the Command Truth Table.
11. Valid commands for Power Down Entry and Exit are Deselect only.
12. Valid commands for Self Refresh Exit are Deselect only. except for Gear Down mode and Max Power Saving exit. NOP is allowed for
these 2 modes.
13. Self Refresh cannot be entered during Read or Write operations. For a detailed list of restrictions see section “Self-Refresh Operation”
and see section “Power-Down Modes”.
14. The Power Down does not perform any refresh operations.
15. “X” means “don't care” (including floating around V
REF
) in Self Refresh and Power Down. It also applies to Address pins.
16. V
PP
and V
REF
(V
REFCA
) must be maintained during Self Refresh operation.
17. If all banks are closed at the conclusion of the read, write or precharge command, then Precharge Power Down is entered, otherwise
Active Power Down is entered.
18. ‘Idle state’ is defined as all banks are closed (t
RP
, t
DAL
, etc. satisfied), no data bursts are in progress, CKE is high, and all timings from
previous operations are satisfied (t
MRD
, t
MOD
, t
RFC
, t
ZQinit
, t
ZQoper
, t
ZQCS
, etc.) as well as all Self Refresh exit and Power Down Exit
parameters are satisfied (t
XS
, t
XP
, etc).
AS4C512M8D4
Confidential
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Rev.1.0. Aug.2019