AS4C512M8D4 Revision History 4Gb DDR4 AS4C512M8D4 - 78 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Aug 2019 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 196 - Rev.1.0. Aug.
AS4C512M8D4 512M x 8 bit DDR4 Synchronous DRAM (SDRAM) Preliminary (Rev. 1.0, Aug.
AS4C512M8D4 Ball Assignment 1 2 3 A VDD VSSQ B VPP C … 7 8 9 TDQS# DM#/DBI# /TDQS VSSQ VSS VDDQ DQS# DQ1 VDDQ ZQ VDDQ DQ0 DQS VDD VSS VDDQ D VSSQ DQ4 DQ2 DQ3 DQ5 VSSQ E VSS VDDQ DQ6 DQ7 VDDQ VSS F VDD NC ODT CK CK# VDD G VSS NC CKE CS# NC NC H VDD WE#/A14 ACT# CAS#/ A15 RAS#/ A16 VSS J VREFCA BG0 A10/AP A12/BC# BG1 VDD K VSS BA0 A4 A3 BA1 VSS L Reset# A6 A0 A1 A5 Alert# M VDD A8 A2 A9 A7 VPP N VSS A11 PAR NC A13
AS4C512M8D4 ALERT# CRC and parity Control Row Decoder Row Decoder ODT 32M x 8 CELL ARRAY (BANK #3) Bank Group 3 Column Decoder 32M x 8 CELL ARRAY (BANK #0) Bank Group 1 Column Decoder 32M x 8 CELL ARRAY (BANK #1) Bank Group 1 Column Decoder 32M x 8 CELL ARRAY (BANK #2) Bank Group 1 Column Decoder 32M x 8 CELL ARRAY (BANK #3) Bank Group 1 Column Decoder DQ Buffer DQ0~DQ7 Row Decoder TDQS, TDQS# Row Decoder DATA STROBE BUFFER DQS, DQS# 32M x 8 CELL ARRAY (BANK #2) Bank Group 3 Column Decoder
AS4C512M8D4 Simplified State Diagram This simplified State Diagram is intended to provide an overview of the possible state transitions and the commands to control them. In particular, situations involving more than on bank, the enabling or disabling of on-die termination, and some other events are not captured in full detail.
AS4C512M8D4 Ball Descriptions Table 3. Ball Details Symbol Type Description CK, CK# Input CKE Input CS# Input Clock: CK and CK# are differential clock inputs. All control and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Clock Enable: CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers.
AS4C512M8D4 Burst Chop: A12/BC# is sampled during Read and Write commands to determine if burst chop (on-the-fly) will be performed. (high, no burst chop; low: burst chopped). See command truth table for details. Active Low Asynchronous Reset: Reset is active when Reset# is low, and inactive when Reset# is high. Reset# must be high during normal operation. Reset# is a CMOS rail-to-rail signal with DC high and low at 80% and 20% of VDD. Data Input/ Output: Bi-directional data bus.
AS4C512M8D4 Basic Functionality The DDR4 SDRAM is a high-speed dynamic random-access memory internally organized with sixteenbanks (4 bank groups each with 4 banks). The DDR4 SDRAM uses a 8n prefetch architecture to achieve highspeed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins.
AS4C512M8D4 3. Clocks (CK, CK#) need to be started and stabilized for at least 10ns or 5t CK (which is larger) before CKE goes active. Since CKE is a synchronous signal, the corresponding setup time to clock (t IS) must be met. Also a Deselect command must be registered (with tIS set up time to clock) at clock edge Td. Once the CKE registered “high” after Reset, CKE needs to be continuously registered “high” until the initialization sequence is finished, including expiration of tDLLK and tZQinit. 4.
AS4C512M8D4 VDD Slew rate at Power-up Initialization Sequence Table 4. VDD Slew Rate Symbol Min. Max. Units Notes VDD_sl 0.004 600 V/ms 1,2 VDD_ona - 200 ms 3 Notes: 1. Measurement made between 300mv and 80% VDD minimum. 2. 20 MHz bandlimited measurement. 3. Maximum time to ramp VDD from 300 mv to VDD minimum. Reset Initialization with Stable Power The following sequence is required for Reset at no power interruption initialization: 1. Asserted Reset# below 0.
AS4C512M8D4 Operation Mode Truth Table Notes 1, 2, 3 and 4 apply to the entire Command Truth Table. Note 5 Applies to all Read/Write commands. [BG=Bank Group Address, BA=Bank Address, RA=Row Address, CA=Column Address, BC#=Burst Chop, X=Don’t Care, V=Valid]. Table 5.
AS4C512M8D4 Table 6.
AS4C512M8D4 Programming the Mode Registers For application flexibility, various functions, features, and modes are programmable in seven Mode Registers, provided by the DDR4 SDRAM, as user defined variables and they must be programmed via a Mode Register Set (MRS) command. The mode registers are divided into various fields depending on the functionality and/or modes. As not all the Mode Registers (MRn) have default values defined, contents of Mode Registers must be initialized and/or re-initialized, i.e.
AS4C512M8D4 The most MRS command to Non-MRS command delay, tMOD, is required for the DRAM to update the features, and is the minimum time required from an MRS command to a non-MRS command excluding DES, as shown in the tMOD timing figure. Some of the mode register setting cases, function updating takes longer than tMOD. The MRS commands that do not apply tMOD timing to next valid command excluding DES is listed in Note 2 of tMOD timing figure.
AS4C512M8D4 Mode Register MR0 Table 7.
AS4C512M8D4 Burst Length, Type and Order Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3 of Mode Register MR0. The ordering of accesses within a burst is determined by the burst length, burst type, and the starting column address as shown in the following table. The burst length is defined by bits A0-A1 of Mode Register MR0.
AS4C512M8D4 Mode Register MR1 Table 9.
AS4C512M8D4 ODT RTT_NOM Values The device is capable of providing three different termination values: R TT_PARK, RTT_NOM, and RTT_WR. The nominal termination value, RTT_NOM, is programmed in MR1. A separate value, RTT_WR, may be programmed in MR2 to enable a unique RTT value when ODT is enabled during Write operations. The RTT_WR value can be applied during Write commands even when RTT_NOM is disabled. A third RTT value, RTT_PARK, is programmed in MR5.
AS4C512M8D4 Mode Register MR2 Table 10.
AS4C512M8D4 Mode Register MR3 Table 11.
AS4C512M8D4 Write Command Latency When CRC/DM is Enabled The Write command latency (WCL) must be set when both Write CRC and DM are enabled for Write CRC persistent mode. This provides the extra time required when completing a Write burst when Write CRC and DM are enabled. Fine Granularity Refresh Mode This mode had been added to DDR4 to help combat the performance penalty due to refresh lockout at high densities.
AS4C512M8D4 Mode Register MR4 Table 12.
AS4C512M8D4 Command Address Latency Command Address Latency (CAL) is a power savings feature and can be enabled or disabled via the MRS setting. CAL is defined as the delay in clock cycles (tCAL) between a CS# registered LOW and its corresponding registered command and address. The value of CAL (in clocks) must be programmed into the mode register and is based on the roundup (in clocks) of [tCK(ns)/tCAL(ns)]. Internal VREF Monitor The device generates its own internal V REFDQ.
AS4C512M8D4 Mode Register MR5 Table 13.
AS4C512M8D4 CA Parity Error Status The device will set the error status bit to 1 upon detecting a parity error. The parity error status bit remains set at 1 until the device controller clears it explicitly using an MRS command. CRC Error Clear The device will set the error status bit to 1 upon detecting a CRC error. The CRC error status bit remains set at 1 until the device controller clears it explicitly using an MRS command.
AS4C512M8D4 Mode Register MR6 Table 14. MR6 Definition BG0 BA1 BA0 1 1 0 A12 A11 A10 RAS# CAS# WE#/ A13 /A16 /A15 A14 0 0 *1 0 tCCD_L.min (tCK) A12 0 A11 A10 A9 A8 *1 tCCD_L 0 A7 A6 A5 A4 VREFDQ VREFDQ *1 0 A3 A2 A1 A0 VREFDQ Training Value Training Range tDLLK.
AS4C512M8D4 Mode Register MR7: Ignore The DDR4 SDRAM shall ignore any access to MR7 for all DDR4 SDRAM. Any bit setting within MR7 may not take any effect in the DDR4 SDRAM. Confidential - 27 of 196 - Rev.1.0. Aug.
AS4C512M8D4 DLL-off Mode and DLL on/off Switching Procedure DLL on/off switching procedure The DLL-off mode is entered by setting MR1 bit A0 to “0”; this will disable the DLL for subsequent operations until A0 bit is set back to “1”. DLL “on” to DLL “off” Procedure To switch from DLL “on” to DLL “off” requires the frequency to be changed during Self-Refresh, as outlined in the following procedure: 1.
AS4C512M8D4 DLL “off” to DLL “on” Procedure To switch from DLL “off” to DLL “on” (with required frequency change) during Self-Refresh: 1. Starting from Idle state (All banks pre-charged, all timings fulfilled and DRAMs On-die Termination resistors (RTT_NOM) must be in high impedance state before Self-Refresh mode is entered.) 2. Enter Self Refresh Mode, wait until tCKSRE satisfied. 3. Change frequency, following the guidelines in the Input Clock Frequency Change section. 4.
AS4C512M8D4 DLL-off Mode DLL-off mode is entered by setting MR1 bit A0 to “0”; this will disable the DLL for subsequent operations until A0 bit is set back to “1”. The MR1 A0 bit for DLL control can be switched either during initialization or during self refresh mode. Refer to the Input Clock Frequency Change section for more details. The maximum clock frequency for DLL-off Mode is specified by the parameter tCKDLL_OFF.
AS4C512M8D4 Input Clock Frequency Change After the device is initialized, the DDR4 SDRAM requires the clock to be “stable” during almost all states of normal operation. This means that after the clock frequency has been set and is to be in the “stable state”, the clock period is not allowed to deviate except for what is allowed for by the clock jitter and SSC (spread spectrum clocking) specifications.
AS4C512M8D4 Write Leveling For better signal integrity, the DDR4 memory module adopted fly-by topology for the commands, addresses, control signals, and clocks. The fly-by topology has benefits from reducing number of stubs and their length, but it also causes flight time skew between clock and strobe at every DRAM on the DIMM. This makes it difficult for the Controller to maintain tDQSS, tDSS, and tDSH specification.
AS4C512M8D4 DRAM setting for write leveling & DRAM termination function in that mode DRAM enters into Write leveling mode if A7 in MR1 set ’High’ and after finishing leveling, DRAM exits from write leveling mode if A7 in MR1 set ’Low’ (see the MR setting involved in the leveling procedure table). Note that in write leveling mode, only DQS terminations are activated and deactivated via ODT pin, unlike normal operation (see the DRAM termination function in the leveling mode table). Table 15.
AS4C512M8D4 Procedure Description The Memory controller initiates Leveling mode of all DRAMs by setting bit A7 of MR1 to 1. When entering write leveling mode, the DQ pins are in undefined driving mode. During write leveling mode, only Deselect commands are allowed, as well as an MRS command to change Qoff bit (MR1[A12]) and an MRS command to exit write leveling (MR1[A7]). Upon exiting write leveling mode, the MRS command performing the exit (MR1[A7]=0) may also change the other MR1 bits.
AS4C512M8D4 Write Leveling Mode Exit The following sequence describes how the Write Leveling Mode should be exited: 1. After the last rising strobe edge (see ~T0), stop driving the strobe signals (see ~Tc0). Note: From now on, DQ pins are in undefined driving mode, and will remain undefined, until tMOD after the respective MRS command (Te1). 2. Drive ODT pin low (tIS must be satisfied) and continue registering low (see Tb0). 3.
AS4C512M8D4 CAL Mode (CS# to Command Address Latency) DDR4 supports Command Address Latency (CAL) function as a power savings feature. CAL is the delay in clock cycles between CS# and CMD/ADDR defined by MR4[A8:A6]. CAL gives the DRAM time to enable the CMD/ADDR receivers before a command is issued. Once the command and the address are latched, the receivers can be disabled. For consecutive commands, the DRAM will keep the receivers enabled for the duration of the command sequence.
AS4C512M8D4 T0 CK# Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 CK Tc0 tCAL CS# tCAL CMD (w/o CS#) tMOD_CAL MRS DES DES DES DES VALID NOTES: 1. MRS at Ta1 may or may not modify CAL, tMOD_CAL is computed based on new tCAL setting. 2. tMOD_CAL = tMOD+tCAL Figure 18. tMOD_CAL, MRS to valid command timing with CAL enabled CK# Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 CK Tc0 tCAL CS# tMRD_CAL CMD (w/o CS#) MRS DES DES DES DES MRS NOTES: 1. MRS command at Ta1 enables CAL mode 2. tMRD_CAL=tMOD+tCAL Figure 19.
AS4C512M8D4 T0 T1 T3 T4 T7 T8 Ta0 T11 Ta7 Ta8 Ta9 Ta10 Tb0 SRX2 DES DES DES Tb1 Tb3 CK# CK tCKSRE tCKSRX CKE CS# CMD w/o CS# DES DES SRE tCAL DES SRE tXS_FAST tCPDED ADDR VALID3 DES tCAL VALID VALID TIME BREAK NOTES: 1. tCAL = 3nCK, tCPDED = 4nCK, tCKSRE = 8nCK, tCKSRX = 8nCK, tXS_FAST = tRFC4(min) + 10ns 2. CS# = H, ACT# = Don't Care, RAS#/A16 = Don't Care, CAS#/A15 = Don't Care, WE#/A14 = Don't Care 3.
AS4C512M8D4 Fine Granularity Refresh Mode DDR4 supports Command Address Latency (CAL) function as a power savings feature. CAL is the delay in clock cycles between CS# and CMD/ADDR defined by MR4[A8:A6]. CAL gives the DRAM time to enable the CMD/ADDR receivers before a command is issued. Once the command and the address are latched, the receivers can be disabled. For consecutive commands, the DRAM will keep the receivers enabled for the duration of the command sequence.
AS4C512M8D4 tREFI and tRFC parameters The default Refresh rate mode is fixed 1x mode where Refresh commands should be issued with the normal rate, i.e., tREFI1 = tREFI(base) (for TCASE ≤ 85°C), and the duration of each refresh command is the normal refresh cycle time (tRFC1). In 2x mode (either fixed 2x or on-the-fly 2x mode), Refresh commands should be issued to the device at the double frequency (t REFI2 = tREFI(base)/2) of the normal Refresh rate.
AS4C512M8D4 Changing Refresh Rate If Refresh rate is changed by either MRS or on the fly, new t REFI and tRFC parameters would be applied from the moment of the rate change. When REF1x command is issued to the DRAM, then tREF1 and tRFC1 are applied from the time that the command was issued. when REF2x command is issued, then t REF2 and tRFC2 should be satisfied. DES REF1 DES DES DES VALID VALID REF2 DES DES VALID DES REF2 DES DES DES tRFC2 (min) tRFC1 (min) tREFI1 tREFI2 Figure 24.
AS4C512M8D4 Usage with Temperature Controlled Refresh mode If the Temperature Controlled Refresh mode is enabled, then only the normal mode (Fixed 1x mode; MR3 [8:6] = 000) is allowed. If any other Refresh mode than the normal mode is selected, then the temperature controlled Refresh mode must be disabled.
AS4C512M8D4 Self Refresh Operation The Self-Refresh command can be used to retain data in the device, even if the rest of the system is powered down. When in the Self-Refresh mode, the device retains data without external clocking. The device has a built-in timer to accommodate Self-Refresh operation. The Self-Refresh-Entry (SRE) Command is defined by having CS#, RAS#/A16, CAS#/A15, and CKE held low with WE#/A14 and ACT# high at the rising edge of the clock.
AS4C512M8D4 Self Refresh Abort The exit timing from self-refresh exit to first valid command not requiring a locked DLL is tXS. The value of tXS is (tRFC+10ns). This delay is to allow for any refreshes started by the DRAM to complete. t RFC continues to grow with higher density devices so tXS will grow as well. A Bit A9 in MR4 is defined to enable the self refresh abort mode. If the bit is disabled then the controller uses tXS timings.
AS4C512M8D4 Low Power Auto Self Refresh (LPASR) DDR4 devices support Low Power Auto Self-Refresh (LPASR) operation at multiple temperatures ranges (See temperature table below) Auto Self Refresh (ASR) DDR4 DRAM provides an Auto Self-Refresh mode (ASR) for application ease. ASR mode is enabled by setting the above MR2 bits A6=1 and A7=1. The device will manage Self Refresh entry through the supported temperature range of the DRAM.
AS4C512M8D4 Self Refresh Exit with No Operation command Self Refresh Exit with No Operation command (NOP) allows for a common command/address bus between active DRAM and DRAM in Max Power Saving Mode. Self Refresh Mode may exit with No Operation commands (NOP) provided: The DRAM entered Self Refresh Mode with CA Parity and CAL disabled. tMPX_S and tMPX_LH are satisfied. NOP commands are only issued during tMPX_LH window. No other command is allowed during tMPX_LH window after SRX command is issued.
AS4C512M8D4 Power down Mode Power-down is synchronously entered when CKE is registered low (along with Deselect command). CKE is not allowed to go low while mode register set command, MPR operations, ZQCAL operations, DLL locking or Read / Write operation are in progress. CKE is allowed to go low while any of other operations such as row activation, precharge or auto-precharge and refresh are in progress, but power-down IDD spec will not be applied until finishing those operations.
AS4C512M8D4 CK# CK CMD T0 T1 Ta0 VALID DES DES tPD tIS Tb0 Tc1 DES DES DES VALID VALID VALID tCKE tIS tIH ADDR Tc0 Td0 tIH CKE ODT2 Tb1 VALID VALID tCPDED tXP Enter Power-Down Mode Exit Power-Down Mode TIME BREAK DON'T CARE NOTE 1. VALID command at T0 is ACT, DES or Precharge with still one bank remaining open after completion of the precharge command. NOTE 2. ODT pin driven to a valid state. MR5 bit A5=0 (default setting) is shown. Figure 27.
AS4C512M8D4 T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 RD or RDA DES DES DES DES DES DES DES DES CK# Ta7 Tb0 Tc0 Tc1 DES DES VALID CK CMD DES tIS tCPDED CKE VALID ADDR VALID VALID tPD RL = AL + CL DQS, DQS# DQ BL8 DQ BC4 tRDPDEN Dout b Dout b+1 Dout b+2 Dout b+3 Dout b Dout b+1 Dout b+2 Dout b+3 Dout b+4 Dout b+5 Dout b+6 Dout b+7 Power - Down Entry TRANSITIONING DATA TIME BREAK DON'T CARE Figure 29.
AS4C512M8D4 CK# CK CMD T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 WRITE DES DES DES DES DES DES DES DES DES DES Tb1 DES tIS Tc0 Td0 Td1 DES DES VALID tCPDED CKE ADDR VALID Bank, Col n VALID tWR WL = AL + CWL tPD A10 DQS, DQS# DQ BL8 Din b Din b+1 Din b+2 Din b+3 DQ BC4 Din b Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 tWRPDEN Power - Down Entry TRANSITIONING DATA TIME BREAK DON'T CARE Figure 31.
AS4C512M8D4 T0 T1 T2 Ta0 Ta1 Tc0 REF DES DES DES DES CK# CK CMD VALID ADDR tCPDED tIS tPD tCKE CKE tREFPDEN TIME BREAK DON'T CARE Figure 33. Refresh Command Power-Down Entry T1 T2 Ta0 Ta1 Tb0 CMD ACTIVE DES DES DES DES ADDR VALID CK# T0 CK tIS tCPDED tPD tCKE CKE tACTPDEN TIME BREAK DON'T CARE Figure 34. Activate Command Power-Down Entry Confidential - 51 of 196 - Rev.1.0. Aug.
AS4C512M8D4 T1 T2 Ta0 Ta1 Tb0 CMD PRE or PREA DES DES DES DES ADDR VALID CK# T0 CK tIS tCPDED tPD tCKE CKE tPRPDEN TIME BREAK DON'T CARE Figure 35. Precharge/Precharge all Command Power-Down Entry CK# T0 T1 Ta0 Tb0 MRS DES DES DES Tb1 Tc0 CK CMD ADDR DES VALID tIS tCPDED tCKE tPD CKE tMRSPDEN TIME BREAK DON'T CARE Figure 36. MRS Command Power-Down Entry Confidential - 52 of 196 - Rev.1.0. Aug.
AS4C512M8D4 Power-Down Clarifications When CKE is registered low for power-down entry, tPD (MIN) must be satisfied before CKE can be registered high for power-down exit. The minimum value of parameter tPD (MIN) is equal to the minimum value of parameter tCKE (MIN) as shown in the timing parameters table. A detailed example of Case 1 is shown below.
AS4C512M8D4 Power Down Entry and Exit timing during Command/Address Parity Mode is Enable Power Down entry and exit timing during Command/Address Parity mode is enable shown below.
AS4C512M8D4 Maximum Power Saving Mode This mode provides lowest power consuming mode which could be similar to the Self-Refresh status with no internal refresh activity. When DDR4 SDRAM is in the maximum power saving mode, it does not need to guarantee data retention nor respond to any external command (except maximum power saving mode exit and asserting RESET# signal LOW) to minimize the power consumption. Maximum Power-Saving Mode Entry Max power saving mode is entered through an MRS command.
AS4C512M8D4 CKE transition during the mode CKE toggle is allowed when DRAM is in the maximum power saving mode. To prevent the device from exiting the mode, CS# should be issued ‘High’ at CKE ‘L’ to ’H’ edge with appropriate setup t MPX_S and hold tMPX_HH timings. CK# CK Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 Tb3 Tc0 Tc1 Tc2 Td0 Td1 Td2 Td3 Td4 Td5 Td6 Td7 CMD tMPX_S CS# tMPX_HH CKE RESET# DON'T CARE Figure 41.
AS4C512M8D4 Table 23. Timing parameter bin of Maximum Power Saving Mode Symbol tMPED Command path disable delay upon MPSM entry tCKMPE Valid clock requirement after MPSM entry tCKMPX Valid clock requirement before MPSM exi tXMP DDR4-2400 Parameter Min. Max. Min. Max.
AS4C512M8D4 Control Gear-down Mode The following description represents the sequence for the gear-down mode which is specified with MR3 A[3]. This mode is allowed just during initialization and self refresh exit. The DRAM defaults in 1/2 rate (1N) clock mode and utilizes a low frequency MRS command followed by a sync pulse to align the proper clock edge for operating the control lines CS#, CKE and ODT in 1/4rate(2N) mode.
AS4C512M8D4 TdkN TdkN + Neven CK# CK CKE tDLLK tGEAR_setup tGEAR_hold tGEAR_setup tGEAR_hold MRS CMD NOP CS# VALID2 2N Mode 1N Sync Pulse tXS or Abort1 tSYNC_GEAR tCMD_GEAR DRAM (Internal) CLK Reset Configure DRAM to 1/4 rate SRX DON'T CARE NOTE 1. CKE High Assert to Gear Down Enable Time (tXS, tXS_Abort) depend on MR setting. A correspondence of tXS/tXS_Abort and MR Setting is as follows. - MR4[A9] = 0 : tXS - MR4[A9] = 1 : tXS_Abort NOTE 2. Command not requiring locked DLL NOTE 3.
AS4C512M8D4 Refresh Command The Refresh command (REF) is used during normal operation of the device. This command is non persistent, so it must be issued each time a refresh is required. The device requires Refresh cycles at an average periodic interval of tREFI. When CS#, RAS#/A16 and CAS#/A15 are held Low and WE#/A14 and ACT# are held High at the rising edge of the clock, the device enters a Refresh cycle.
AS4C512M8D4 Data Mask (DM), Data Bus Inversion (DBI) and TDQS DDR4 SDRAM supports Data Mask (DM) function and Data Bus Inversion (DBI) function in x8 configuration. x8 DDR4 SDRAM supports TDQS function. DM, DBI & TDQS functions are supported with dedicated one pin labeled as DM#/DBI#/TDQS. The pin is bidirectional pin for DRAM. The DM#/DBI# pin is Active Low as DDR4 supports VDDQ reference termination. TDQS function does not drive actual level on the pin.
AS4C512M8D4 ZQ Calibration Commands ZQ Calibration command is used to calibrate DRAM RON & ODT values. The device needs longer time to calibrate output driver and on-die termination circuits at initialization and relatively smaller time to perform periodic calibrations. ZQCL command is used to perform the initial calibration during power-up initialization sequence. This command may be issued at any time by the controller depending on the system environment.
AS4C512M8D4 Tb1 Tc0 Tc1 T0 T1 Ta0 Ta1 Ta2 Ta3 Tb0 ZQCL DES DES DES VALID VALID ZQCS ADDR VALID VALID VALID A10 VALID VALID VALID VALID VALID VALID VALID CK# Tc2 CK CMD CKE ODT DQ Bus Notes 1 Notes 2 Notes 3 Hi-Z or RTT_PARK ACTIVITIES DES DES DES VALID Notes 1 Notes 2 Notes 3 tZQinit or tZQoper VALID VALID Hi-Z or RTT_PARK tZQCS TIME BREAK NOTE 1. CKE must be continuously registered high during the calibration procedure. NOTE 2.
AS4C512M8D4 DQ VREF Training The DRAM internal DQ VREF specification parameters are operating voltage range, stepsize, V REF step time, VREF full step time and VREF valid level. The voltage operating range specifies the minimum required V REF setting range for DDR4 DRAM devices. The minimum range is defined by VREFmax and VREFmin as depicted in the following figure. VDDQ VREFmax VREF Range VREFmin Vswing Small System Variance Vswing Large Total Range Figure 48.
AS4C512M8D4 The VREF increment/decrement step times are defined by VREF_time. The VREF_time is defined from t0 to t1, where t1 is referenced to when the VREF voltage is at the final DC level within the VREF valid tolerance (VREF_val_tol). The VREF valid level is defined by VREF_val tolerance to qualify the step time t1. This parameter is used to insure an adequate RC time constant behavior of the voltage level change after any Vref increment/decrement adjustment.
AS4C512M8D4 Table 26. AC parameters of VREFDQ training Symbol Parameter Min. Max.
AS4C512M8D4 VREF Voltage VREF (VDDQ DC) VREFmax VREF_val_tol Full Range Step t1 VREFmin Time Figure 54. VREF full step from VREFmin to VREFmax case VREF Voltage VREFmax Full Range Step t1 VREF_val_tol VREF (VDDQ DC) VREFmin Time Figure 55. VREF full step from VREFmax to VREFmin case Table 27.
AS4C512M8D4 Per DRAM Addressability DDR4 allows programmability of a given device on a rank. As an example, this feature can be used to program different ODT or VREF values on DRAM devices on a given rank. 1. Before entering ‘per DRAM addressability (PDA)’ mode, the write leveling is required. BL8 or BC4 may be used. 2. Before entering ‘per DRAM addressability (PDA)’ mode, the following Mode Register setting is possible. RTT_PARK MR5 A[8:6] = Enable RTT_NOM MR1 A[10:8] = Enable 3.
AS4C512M8D4 CK# CK MRS tMOD_PDA AL + CWL + PL VALID DODTLoff = WL - 3 ODT RTT_PARK RTT RTT_NOM RTT_PARK DODTLOn = WL - 3 DQS, DQS# DQ0 (selected device) tPDA_S tPDA_H MR3 A4 = 0 (PDA Disable) NOTE: RTT_PARK = Enable, RTT_NOM = Enable, Write Preamble Set = 2tCK and DLL = ON, CA parity is used. Figure 57. MRS w/ per DRAM addressability (PDA) Exit CK# CK MRS tMOD MRS tMRD_PDA AL + CWL + PL MRS DQS, DQS# DQ0 (selected device) tPDA_S tPDA_H MR3 A4 = 1 (PDA Enable) NOTE: CA parity is used..
AS4C512M8D4 Command Address Parity (CA Parity) [A2:A0] of MR5 are defined to enable or disable C/A Parity in the DRAM. The default state of the C/A Parity bits is disabled. If C/A parity is enabled by programming a non-zero value to C/A Parity Latency in the mode register (the Parity Error bit must be set to zero when enabling C/A any Parity mode), then the DRAM has to ensure that there is no parity error before executing the command.
AS4C512M8D4 Table 29. Mode Registers for C/A Parity C/A Parity Latency MR5[2:0]* Speed bins 000 = Disabled - 001= 4 Clocks 1600,1866,2133 010= 5 Clocks 2400,2666 011= 6 Clocks RFU 100= 8 Clocks RFU C/A Parity Error Status MR5[4] Errant C/A Frame 0 = Clear ACT#, BG1, BG0, BA0, BA1, PAR, A16/RAS#, A15/CAS#, A14/WE#, A13:A0 1 = Error Note 1. Parity Latency is applied to all commands. Note 2. Parity Latency can be changed only from a C/A Parity disabled state, i.e.
AS4C512M8D4 CK# T0 T1 ERROR2 DES1 CK CMD/ ADDR Ta0 Ta1 Tb0 Tb1 Tc0 Tc1 Td0 Td1 Td2 Td3 Te0 Te1 DES5 DES5 DES REF4 VALID3 tCPDED DES1 tPAR_ALERT_ON tPAR_ALERT_PW1 ALERT# t≧2nCK tIS CKE tIH tRP tIS DES REF4 DES5 Command execution unknown ERROR2 DES1 Command not executed TIME BREAK DON'T CARE Command executed VALID3 NOTE 1. Deselect command only allowed. NOTE 2. Error could be Precharge or Activate. NOTE 3.
AS4C512M8D4 CK# T0 Ta0 Ta1 SRX1 DES DES Tb0 Tb1 Tc0 Tc1 ERROR VALID2 VALID2 VALID2 Tc2 Td0 Td1 Te0 Tf0 CK CMD/ ADDR ALERT# tPAR_UNKNOWN tPAR_ALERT_ON DES REF2 2,4,6 2,4,5 DES REF2,3 t≧2nCK VALID VALID 2,4,7 VALID tRP tPAR_ALERT_PW tXS_FAST8 tIS CKE tXS tXSDLL DES(1,5) DES6 ERROR2 DES1 DES REF5 TIME BREAK Command execution unknown DON'T CARE Command not executed Command executed VALID3 NOTE 1.
AS4C512M8D4 CK# Ta0 Ta1 Ta2 Tb0 DES MRS DES DES Tb1 Tb2 CK CMD Settings PL = 0 VALID Updating Setting DES PL = N tMOD_PAR Enable Parity change PL from 0 to N NOTE 1. tMOD_PAR = tMOD + N; where N is the programmed parity latency with the MRS command entering CA parity mode. NOTE 2. Parity check is not available at Ta1 of MRS command due to PL=0 being valid. NOTE 3. In case parity error happens at Tb1 of VALID command, tPAR_ALERT_ON is ‘N[nCK] + 6[ns]’. Figure 65.
AS4C512M8D4 Multipurpose Register The Multipurpose Register (MPR) function, MPR access mode, is used to write/read specialized data to/from the DRAM. The MPR consists of four logical pages, MPR Page 0 through MPR Page 3, with each page having four 8-bit registers, MPR0 through MPR3. MPR mode enable and page selection is done with MRS commands. Data bus inversion (DBI) is not allowed during MPR Read operation.
AS4C512M8D4 Table 31.
AS4C512M8D4 MPR Reads MPR reads are supported using BL8 and BC4 modes. Burst length on-the-fly is not supported for MPR reads. Data bus inversion (DBI) is not allowed during MPR Read operation; the device will ignore the Read DBI enable setting in MR5 [A12] when in MPR mode. Read commands for BC4 are supported with a starting column address of A[2:0] = 000 or 100. After power-up, the content of MPR Page 0 has the default values, which are defined in MPR Data Format table.
AS4C512M8D4 MPR Readout Serial Format The serial format is required when enabling the MPR function to read out the contents of an MRx, temperature sensor status, and the command address parity error frame. However, data bus calibration locations (four 8-bit registers) can be programmed to read out any of the three formats. The DRAM is required to drive associated strobes with the read data similar to normal operation (such as using MRS preamble settings).
AS4C512M8D4 MPR Readout Parallel Format Parallel format implies that the MPR data is returned in the first data UI and then repeated in the remaining UIs of the burst, as shown in the table below. Data pattern location 0 is the only location used for the parallel format. RD/RDA from data pattern locations 1, 2, and 3 are not allowed with parallel data return mode. In this example, the pattern programmed in the data pattern location 0 is 0111 1111.
AS4C512M8D4 MPR Readout Staggered Format Staggered format of data return is defined as the staggering of the MPR data across the lanes. In this mode, an RD/RDA command is issued to a specific data pattern location and then the data is returned on the DQ from each of the different data pattern locations.
AS4C512M8D4 MPR Read Waveforms T0 Ta0 Ta1 Tb0 Tc0 Tc1 Tc2 Tc3 Td0 Td1 Te0 Tf0 CK# CK MPR Disable MPR Enable CMD PREA MRS 1 DES tRP RD DES DES DES DES DES MRS3 DES tMOD tMPRR VALID4 tMOD CKE DQS# DQS PL5 + AL + CL ADDR VALID VALID ADD2 VALID VALID VALID VALID DQs VALID UI0 UI1 VALID UI2 UI5 VALID UI6 VALID VALID UI7 NOTE 1. Multi-Purpose Registers Read/Write Enable (MR3 A2 = 1) - Redirect all subsequent read and writes to MPR locations NOTE 2.
AS4C512M8D4 T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 DES DES DES DES DES DES DES DES Tb0 Tb1 WR DES CK# CK CMD RD DES tMPRR CKE DQS# DQS ADDR PL3 + AL + CL ADD DQs 1 VALID VALID VALID VALID VALID UI0 VALID UI1 UI2 VALID UI3 UI4 VALID UI5 UI6 VALID ADD 2 VALID UI7 TIME BREAK Don't Care NOTE 1.
AS4C512M8D4 MPR Writes MPR access mode allows 8-bit writes to the MPR Page 0 using the address bus A[7:0]. Data bus inversion (DBI) is not allowed during MPR Write operation. The DRAM will maintain the new written values unless reinitialized or there is power loss. The following steps are required to use the MPR to write to mode register MPR Page 0. 1. The DLL must be locked if enabled. 2. Precharge all; wait until tRP is satisfied. 3.
AS4C512M8D4 MPR Write Waveforms CK# T0 Ta0 CK CMD Ta1 Tb0 Tc0 Tc1 Tc2 Td0 Td1 Td2 Td3 Td4 Td5 DES WR DES DES RD DES DES DES DES DES DES VALID VALID VALID VALID VALID MPR Enable PREA MRS1 tRP tMOD tWR_MPR CKE PL3 + AL + CL ADDR VALID VALID VALID ADD2 VALID VALID ADD VALID DQS# DQS DQ UI0 UI1 UI2 UI3 UI4 TIME BREAK NOTE 1. Multi-Purpose Registers Read/Write Enable (MR3 A2 = 1) NOTE 2.
AS4C512M8D4 MPR Refresh Waveforms T0 Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 DES REF2 DES DES DES Tc2 Tc4 Tb4 Tc0 Tc1 Tc3 DES DES DES VALID VALID VALID VALID VALID VALID VALID VALID VALID CK# CK MPR Enable CMD PREA ADDR VALID MRS1 tRP tRFC tMOD VALID VALID VALID VALID VALID VALID TIME BREAK NOTE 1. Multi-Purpose Registers Read/Write Enable (MR3 A2 = 1) - Redirect all subsequent read and writes to MPR locations NOTE 2. 1x Refresh is only allowed when MPR mode is Enable.
AS4C512M8D4 DDR4 Key Core Timing CK# T0 T1 T2 T3 WRITE DES DES DES T4 T5 WRITE DES T9 T10 T11 T12 T13 DES WRITE DES DES DES CK CMD tCCD_S Bank Group (GB) Bank ADDR DES tCCD_L BG a BG b BG b Bank c Bank c Bank c Col n Col n Col n TIME BREAK DON'T CARE NOTE 1. tCCD_S : CAS#-to-CAS# delay (short) : Applies to consecutive CAS# to different Bank Group (i.e., T0 to T4). NOTE 2. tCCD_L : CAS#-to-CAS# delay (long) : Applies to consecutive CAS# to the same Bank Group (i.e.
AS4C512M8D4 T0 CK# Ta0 Tb0 Tc0 Tc1 ACT VALID Td0 Td1 ACT DES CK CMD ACT VALID ACT VALID tRRD ACT VALID tRRD tRRD VALID tFAW Bank Group (GB) VALID VALID VALID VALID VALID Bank VALID VALID VALID VALID VALID ADDR VALID VALID VALID VALID VALID TIME BREAK DON'T CARE NOTE 1. tFAW: Four activate window. Figure 79.
AS4C512M8D4 Programmable Preamble The DQS preamble can be programmed to one or the other of 1 tCK and 2 tCK preamble; selectable via MRS (MR4 A[12:11]). The 1 tCK preamble applies to all speed-Grade and The 2 tCK preamble is valid for DDR42400/2666 speed-Grade. Write Preamble DDR4 supports a programmable write preamble. The 1 tCK or 2 tCK Write Preamble is selected via MR4 A[12]. Write preamble modes of 1 tCK and 2 tCK are shown below.
AS4C512M8D4 1tCK mode WR WR CK# CK tCCD = 5 WL Preamble Preamble DQS,DQS# DQ D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 2tCK mode: tCCD=5 is not allowed in 2tCK mode Figure 84. tCCD=5 (AL=PL=0) 1tCK mode WR WR CK# CK tCCD = 6 WL Preamble Preamble DQS,DQS# DQ D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D0 D1 D2 D3 2tCK mode WR WR CK# CK tCCD = 6 DQS,DQS# DQ WL Preamble Preamble D0 D1 D2 D3 D4 D5 D6 D7 Figure 85. tCCD=6 (AL=PL=0) Confidential - 89 of 196 - Rev.
AS4C512M8D4 Read Preamble DDR4 supports a programmable read preamble. The 1 tCK and 2 tCK Read preamble is selected via MR4 A[11]. Read preamble modes of 1 tCK and 2 tCK are shown as follows: Preamble DQS, DQS# 1tCK toggle DQ D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Preamble DQS, DQS# 2tCK toggle DQ Figure 86. 1tCK vs.
AS4C512M8D4 Postamble Read Postamble Whether the 1 tCK or 2 tCK Read Preamble Mode is selected, the Read Postamble remains the same at 1/2 tCK. DDR4 will support a fixed read postamble. Read postamble of nominal 0.5 tCK for preamble modes 1,2 tCK are shown below: Preamble Postamble Preamble Postamble DQS, DQS# 1tCK toggle DQ DQS, DQS# 2tCK toggle DQ Figure 88. READ Postamble Write Postamble Whether the 1 tCK or 2 tCK Write preamble mode is selected, the Write postamble remains the same at 1/2 tCK.
AS4C512M8D4 Activate Command The Activate command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BG0-BG1 in x8 select the bank group; BA0-BA1 inputs selects the bank within the bank group, and the address provided on inputs A0-A14 selects the row. This row remains active (or open) for accesses until a precharge command is issued to that bank or a precharge all command is issued. A bank must be precharged before opening a different row in the same bank.
AS4C512M8D4 Read Operation Read Timing Definitions Read timings are shown below and are applicable in normal operation mode, i.e. when the DLL is enabled and locked. Rising data strobe edge parameters: tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK, CK#. tDQSCK is the actual position of a rising strobe edge relative to CK, CK#. tQSH describes the DQS, DQS# differential output high time. tDQSQ describes the latest valid transition of the associated DQ pins.
AS4C512M8D4 Read Timing; Clock to Data Strobe relationship The clock to data strobe relationship is shown below and is applicable in normal operation mode, i.e. when the DLL is enabled and locked. Rising data strobe edge parameters: tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK, CK#. tDQSCK is the actual position of a rising strobe edge relative to CK, CK#. tQSH describes the data strobe high pulse width.
AS4C512M8D4 Read Timing; Data Strobe to Data relationship The Data Strobe to Data relationship is shown below and is applied when the DLL is enabled and locked. Rising data strobe edge parameters: tDQSQ describes the latest valid transition of the associated DQ pins. tQH describes the earliest invalid transition of the associated DQ pins. Falling data strobe edge parameters: tDQSQ describes the latest valid transition of the associated DQ pins.
AS4C512M8D4 tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation tHZ and tLZ transitions occur in the same time window as valid data transitions. These parameters are referenced to a specific voltage level that specifies when the device output is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS), tLZ(DQ). tLZ shows a method to calculate the point when the device is no longer driving t HZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS), tLZ(DQ), by measuring the signal at two different voltages.
AS4C512M8D4 Read Burst Operation DDR4 Read command supports bursts of BL8 (fixed), BC4 (fixed), and BL8/BC4 on-the-fly (OTF); OTF uses address A12 to control OTF during the Read or Write (auto-precharge can be enabled or disabled). A12 = 0, BC4 (BC4 = burst chop) A12 = 1, BL8 Read commands can issue precharge automatically with a read with auto-precharge command (RDA); and is enabled by A10 high. Read command with A10 = 0 (RD) performs standard Read, bank remains active after read burst.
AS4C512M8D4 T0 CK# T1 T4 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 DES READ DES DES DES DES DES DES DES DES DES DES DES DES CK READ CMD tCCD_S = 4 Bank Group ADDR BG a BG b ADDR Bank, Col n Bank, Col b tRPST tRPRE DQS, DQS# DQ Dout n RL = 11 Dout n+1 Dout n+2 Dout n+3 Dout n+4 Dout n+5 Dout n+6 Dout n+7 Dout b Dout b+1 Dout b+2 RL = 11 Dout b+3 Dout b+4 Dout b+5 Dout b+6 TRANSITIONING DATA Dout b+7 DON'T CARE NOTE 1.
AS4C512M8D4 T0 CK# T1 T5 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 DES READ DES DES DES DES DES DES DES DES DES DES DES DES CK READ CMD tCCD_S/L = 5 Bank Group ADDR BG a ADDR Bank, Col n BG a or BG b Bank, Col b tRPST tRPRE DQS, DQS# DQ Dout n RL = 11 Dout n+1 Dout n+2 Dout n+3 Dout n+4 Dout n+5 Dout n+6 Dout n+7 Dout b Dout b+1 Dout b+2 Dout b+3 Dout b+4 Dout b+5 Dout b+6 Dout b+7 RL = 11 DON'T CARE TRANSITIONING DATA NOTE 1.
AS4C512M8D4 CK# T0 T1 T4 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 DES READ DES DES DES DES DES DES DES DES DES DES DES DES CK CMD READ tCCD_S = 4 Bank Group ADDR BG a BG b ADDR Bank, Col n Bank, Col b tRPRE tRPST tRPST tRPRE DQS, DQS# DQ Dout n RL = 11 Dout n+1 Dout n+2 Dout n+3 Dout b Dout b+1 Dout b+2 Dout b+3 DON'T CARE TRANSITIONING DATA RL = 11 NOTE 1. BL = 8, AL = 0, CL = 11, Preamble = 1tCK NOTE 2.
AS4C512M8D4 CK# T0 T1 T8 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 READ DES WRITE READ DES DES DES DES DES DES DES DES DES DES DES CK T22 tWR CMD Bank Group ADDR BG a BG a or BG b ADDR Bank, Col n Bank, Col b tRPRE tRPST DES tWTR 4 Clocks READ to WRITE Command Delay = RL +BL/2 - WL + 2t CK tWPST tWPRE DQS, DQS# DQ Dout n RL = 11 Dout n+1 Dout n+2 Dout n+3 Dout n+4 Dout n+5 Dout n+7 Dout n+6 Din b Din b+1 Din b+2 Din b+3 WL = 9 Din b+4 D
AS4C512M8D4 CK# T0 T1 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T19 READ DES WRITE DES READ DES DES DES DES DES DES DES DES DES DES T20 CK tWR CMD Bank Group ADDR BG a BG a or BG b ADDR Bank, Col n Bank, Col b DES tWTR 4 Clocks READ to WRITE Command Delay = RL +BL/2 - WL + 2t CK tRPRE tRPST tWPST tWPRE DQS, DQS# DQ Dout n RL = 11 Dout n+1 Dout n+2 Dout n+3 Din b Din b+1 Din b+2 Din b+3 WL = 9 DON'T CARE TRANSITIONING DATA NOTE 1.
AS4C512M8D4 CK# T0 T1 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 READ DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES CK CMD T19 tWR Bank Group ADDR BG a BG a or BG b ADDR Bank, Col n Bank, Col b tRPRE tRPST DES tWTR 2 Clocks READ to WRITE Command Delay = RL +BL/2 - WL + 2t CK tWPST tWPRE DQS, DQS# DQ Dout n RL = 11 Dout n+1 Dout n+2 Dout n+3 Din b Din b+1 WL = 9 Din b+2 Din b+3 TRANSITIONING DATA DON'T CARE NOTE 1.
AS4C512M8D4 CK# T1 T4 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 DES READ DES DES DES DES DES DES DES DES DES DES DES DES DES T0 CK CMD READ tCCD_S = 4 Bank Group ADDR BG a BG b ADDR Bank, Col n Bank, Col b tRPST tRPRE DQS, DQS# DQ Dout n RL = 11 Dout n+1 Dout n+2 Dout n+3 Dout n+4 Dout n+5 Dout n+6 Dout n+7 Dout b Dout b+1 Dout b+2 Dout b+3 DON'T CARE TRANSITIONING DATA RL = 11 NOTE 1. BL = 8, AL =0, CL = 11 ,Preamble = 1tCK NOTE 2.
AS4C512M8D4 CK# T0 T1 T4 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 READ DES WRITE DES READ DES DES DES DES DES DES DES DES DES DES CK T19 tWR CMD Bank Group ADDR BG a BG a or BG b ADDR Bank, Col n Bank, Col b tRPRE tRPST DES tWTR 4 Clocks READ to WRITE Command Delay = RL +BL/2 - WL + 2t CK tWPST tWPRE DQS, DQS# DQ Dout n RL = 11 Dout n+1 Dout n+2 Dout n+3 Din b WL = 9 Din b+1 Din b+2 Din b+3 TRANSITIONING DATA DON'T CARE NOTE 1.
AS4C512M8D4 CK# T0 T1 T6 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 READ DES WRITE DES DES DES DES DES DES DES DES DES DES DES CK CMD T20 tWR Bank Group ADDR BG a BG a or BG b ADDR Bank, Col n Bank, Col b tRPRE tRPST DES tWTR 4 Clocks READ to WRITE Command Delay = RL +BL/2 - WL + 2t CK tWPST tWPRE DQS, DQS# DQ Dout n RL = 11 Dout n+1 Dout n+2 Dout n+3 Din b Din b+1 Din b+2 Din b+3 WL = 9 Din b+4 Din b+5 Din b+6 Din b+7 DON'T CARE TRANSITIONING
AS4C512M8D4 CK# T0 T1 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T21 READ DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES CK CMD T22 tWR Bank Group ADDR BG a BG a or BG b ADDR Bank, Col n Bank, Col b tRPRE tRPST DES tWTR 4 Clocks READ to WRITE Command Delay = RL +BL/2 - WL + 2t CK tWPST tWPRE DQS, DQS# DQ Dout n RL = 11 Dout n+1 Dout n+2 Dout n+3 Dout n+4 Dout n+5 Dout n+6 Dout n+7 Din b WL = 9 Din b+1 Din b+2 Din b+3 TRANSITIONIN
AS4C512M8D4 Burst Read Operation followed by a Precharge The minimum external Read command to Precharge command spacing to the same bank is equal to AL + tRTP with tRTP being the Internal Read Command to Precharge Command Delay. Note that the minimum ACT to PRE timing, tRAS, must be satisfied as well.
AS4C512M8D4 CK# T0 T1 T2 T3 T10 T13 T16 T19 T20 T21 T22 T23 T24 T25 T26 T27 DES READ DES DES DES DES PRE DES DES DES DES DES DES DES DES ACT CK CMD Bank a Col n ADDR Bank a (or all) Bank a Row b tRTP AL = CL - 2 = 9 tRP CL = 11 BC4 Operation: DQS, DQS# DQ Dout n Dout n+1 Dout n+2 Dout n+3 Dout n Dout n+1 Dout n+2 Dout n+3 BC8 Operation: DQS, DQS# DQ Dout n+4 Dout n+5 Dout n+6 Dout n+7 DON'T CARE TRANSITIONING DATA NOTE 1.
AS4C512M8D4 CK# T0 T1 T2 T9 T10 T11 T12 T16 T19 T20 T21 T22 T23 T24 T25 T27 DES RDA DES DES DES DES DES DES DES DES DES DES DES DES DES ACT CK CMD Bank a Col n ADDR Bank a Row b tRTP AL = CL – 2 = 9 tRP CL = 11 BC4 Operation: DQS, DQS# DQ Dout n Dout n+1 Dout n+2 Dout n+3 Dout n Dout n+1 Dout n+2 Dout n+3 BC8 Operation: DQS, DQS# DQ NOTE 1. BL = 8, RL = 20 (CL = 11 , AL = CL- 2 ), Preamble = 1tCK, tRTP = 6, tRP = 11 NOTE 2.
AS4C512M8D4 Burst Read Operation with Command/Address Parity CK# T1 T2 T4 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 DES DES READ DES DES DES DES DES DES DES DES DES DES DES DES T0 CK CMD READ tCCD_S = 4 Bank Group ADDR BG a BG b ADDR Prity Bank Col n Bank Col b RL = 15 tRPRE tRPST DQS, DQS# DQ Dout n Dout n+1 Dout n+2 Dout n+3 Dout n+4 Dout n+5 Dout n+6 Dout n+7 Dout b Dout b+1 Dout b+2 Dout b+3 Dout b+4 Dout b+5 Dout b+6 Dout b+7 RL = 15 D
AS4C512M8D4 Read to Write with Write CRC CK# T0 T1 T8 T9 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 READ DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES CK T22 tWR CMD Bank Group ADDR BG a BG a or BG b ADDR Bank Col n Bank Col b DES tWTR 4 Clocks READ to WRITE Command Delay = RL +BL/2 - WL + 2t CK RL = 11 tRPST tRPRE tWPST tWPRE DQS, DQS# BL = 8 DQ Dout n Dout n+1 Dout n+2 Dout n Dout n+1 Dout n+2 Dout n+3 Dout n+4 Dout n+5 Dout n+6 D
AS4C512M8D4 Read to Read with CS to CA Latency T0 CK# CK T1 T3 T4 T5 T6 DES T8 T13 T14 T15 T17 T18 T19 T21 T22 T23 DES DES DES DES DES DES DES DES DES DES tCAL = 3 tCAL = 3 CMD w/o CS# T7 READ DES DES READ CS# Bank Group ADDR BG a BG b tCCD_S = 4 Bank, Col n ADDR Bank, Col b tRPST tRPRE DQS, DQS# RL = 11 DQ Dout n RL = 11 Dout n+1 Dout n+2 Dout n+5 Dout n+6 Dout n+7 Dout b Dout b+1 Dout b+2 Dout b+5 Dout b+6 TRANSITIONING DATA NOTE 1.
AS4C512M8D4 Write Operation Write Timing Definitions This drawing is for example only to enumerate the strobe edges that “belong” to a Write burst. No actual timing violations are shown here. For a valid burst all timing parameters for each edge of a burst need to be satisfied (not only for one edge - as shown).
AS4C512M8D4 T0 T1 T2 T8 CMD3 WRITE DES DES DES 4 BG,Bank CK# T9 T10 T11 T12 T13 T14 T15 DES DES DES DES DES DES CK DES WL = AL + CWL ADD Col n tDQSS(min) tDQSS tDSH tWPRE tDSH tDSH tDSH tWPST DQS, DQS# tDQSH(min) tDQSL tDQSL tDQSH tDQSS(nominal) tDQSH tDQSL tDSS tDSH tWPRE tDQSH tDQSL tDSS tDSS tDQSH tDSS tDSH tDSH tDQSL(min) tDSS tDSH tWPST DQS, DQS# tDQSH(min) tDQSL tDQSH tDSS tDQSS tDQSS(max) tWPRE tDQSL tDSS tDQSH tDSH tDQSL tDSS tDQSH tD
AS4C512M8D4 Write Burst Operation The following write timing diagram is to help understanding of each write parameter's meaning and just examples. The details of the definition of each parameter will be defined separately. In these write timing diagram, CK and DQS are shown aligned and also DQS and DQ are shown center aligned for illustration purpose.
AS4C512M8D4 CK# T0 T1 T4 T7 T8 T9 T10 T12 T11 T13 T14 T15 DES DES T16 T17 DES DES CK T18 T19 DES DES tWR CMD WRITE DES WRITE DES DES DES DES DES DES DES tWTR 4 Clocks tCCD_S = 4 Bank Group ADDR BG a BG b ADDR Bank Col n Bank Col b tWPST tWPRE DQS, DQS# WL = AL + CWL = 9 Din n DQ Din n+1 Din n+2 Din n+3 Din n+4 Din n+5 Din n+6 Din n+7 Din b Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 NOTE 1.
AS4C512M8D4 CK# T0 T1 T5 T8 T9 T10 T11 T13 T12 T15 T14 T16 T18 T17 CK T19 T20 DES DES tWR CMD WRITE DES WRITE DES DES DES DES DES DES DES DES DES DES DES tWTR 4 Clocks tCCD_S/L = 5 Bank Group ADDR BG a BG a or BG b ADDR Bank Col n Bank Col b tWPST tWPRE DQS, DQS# WL = AL + CWL = 9 Din n DQ Din n+1 Din n+2 Din n+3 Din n+4 Din n+5 Din n+6 Din n+7 Din b Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 WL = AL + CWL = 9 DON'T CARE TRANSITION
AS4C512M8D4 T0 CK# T1 T4 T7 T8 T9 T10 T12 T11 T14 T13 T15 T16 T17 CK T18 T19 DES DES tWR WRITE CMD DES WRITE DES DES DES DES DES DES DES DES DES DES DES tWTR 4 Clocks tCCD_S = 4 Bank Group ADDR BG a BG b ADDR Bank Col n Bank Col b tWPST tWPRE DQS, DQS# WL = AL + CWL = 9 Din n DQ Din n+1 Din n+2 Din n+3 Din b Din b+1 Din b+2 Din b+3 WL = AL + CWL = 9 DON'T CARE TRANSITIONING DATA NOTE 1. BC = 4, AL = 0, CWL = 9 , Preamble = 1tCK NOTE 2.
AS4C512M8D4 T0 CK# T1 T4 T7 T8 T9 T10 T12 T11 T14 T13 T15 T17 T16 CK T18 T19 DES DES tWR WRITE CMD DES WRITE DES DES DES DES DES DES DES DES DES DES DES tWTR 2 Clocks tCCD_S = 4 Bank Group ADDR BG a BG b ADDR Bank Col n Bank Col b tWPST tWPRE DQS, DQS# WL = AL + CWL = 9 Din n DQ Din n+1 Din n+2 Din n+3 Din b Din b+1 Din b+2 Din b+3 DON'T CARE TRANSITIONING DATA NOTE 1. BC = 4, AL = 0, CWL = 9 , Preamble = 1tCK NOTE 2.
AS4C512M8D4 CK# T0 T1 T7 T8 T9 T10 WRITE DES DES DES DES DES T11 T12 T13 DES DES DES T16 T17 T18 T26 T27 T28 T29 READ READ DES DES DES DES DES CK CMD tWTR_L = 4 4 Clocks Bank Group ADDR BG a ADDR Bank, Col n BG b Bank, Col b tWPRE tWPST tRPRE DQS, DQS# DQ Din n WL = AL + CWL = 9 Din n+1 Din n+2 Din n+3 Din n+4 Din n+5 Din n+6 Din n+7 Din b RL = AL + CL = 11 NOTE 1. BL = 8, AL = 0, CWL = 9, CL = 11, Preamble = 1tCK NOTE 2.
AS4C512M8D4 CK# T0 T1 T7 T8 T9 T10 T11 T12 T13 T15 T16 T17 T20 T27 T28 T29 WRITE DES DES DES DES DES DES DES DES DES DES READ DES DES DES DES CK CMD tWTR_L = 4 4 Clocks Bank Group ADDR BG a BG b ADDR Bank Col n Bank Col b tWPST tWPRE tRPRE DQS, DQS# WL = AL + CWL = 9 RL = AL + CL = 11 Din n DQ Din n+1 Din n+2 Din n+3 Din b NOTE 1. BC = 4, AL = 0, CWL = 9, CL = 11, Preamble = 1tCK NOTE 2. Din n = data-in to column n (or column b).
AS4C512M8D4 CK# T0 T1 T7 T8 T9 WRITE DES DES DES DES T10 T11 T12 T13 T15 DES DES DES DES READ T16 T24 T25 T26 T27 T28 DES DES DES DES DES DES CK CMD tWTR_L = 4 2 Clocks Bank Group ADDR BG a BG b ADDR Bank Col n Bank Col b tWPST tWPRE tRPST tRPRE DQS, DQS# WL = AL + CWL = 9 RL = AL + CL = 11 Din n DQ Din n+1 Din n+2 Din n+3 Din b NOTE 1. BC = 4, AL = 0, CWL = 9, CL = 11, Preamble = 1tCK NOTE 2. Din n = data-in to column n (or column b).
AS4C512M8D4 CK# T0 T1 T4 T7 T8 T9 T10 T12 T11 T14 T13 T15 T16 T17 DES DES CK T18 T19 DES DES tWR CMD WRITE DES WRITE DES DES DES DES DES DES DES DES DES tWTR 4 Clocks tCCD_S = 4 Bank Group ADDR BG a BG b ADDR Bank Col n Bank Col b tWPST tWPRE DQS, DQS# WL = AL + CWL = 9 Din n DQ Din n+1 Din n+2 Din n+3 Din b Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 WL = AL + CWL = 9 DON'T CARE TRANSITIONING DATA NOTE 1.
AS4C512M8D4 CK# T0 T1 T2 WRITE DES DES T3 T7 T8 T9 DES DES DES DES T10 T11 T12 DES DES DES T13 T14 T23 T24 DES DES PRE DES T25 T26 DES DES CK CMD WL = AL + CWL = 9 ADDR tRP tWR = 12 2 Clocks BGa,Bankb BGa,Bank b Col n (or all) BC4(Fixed) Operation: DQS, DQS# Din n DQ Din n+1 Din n+2 Din n+3 NOTE 1. BC = 4, AL = 0, CWL = 9, Preamble = 1tCK, tWR = 12 NOTE 2. Din n = data-in to column n. NOTE 3.
AS4C512M8D4 CK# T0 T1 T2 WRA DES DES T3 T7 T8 T9 DES DES DES DES T10 T11 T12 DES DES DES T13 T14 T23 T24 DES DES DES DES T25 T26 DES DES CK CMD WL = AL + CWL = 9 ADDR tRP WR = 12 2 Clocks BGa,Bank b Col n BC4(Fixed) Operation: DQS, DQS# Din n DQ Din n+1 Din n+2 Din n+3 TRANSITIONING DATA NOTE 1. BC = 4, AL = 0, CWL = 9, Preamble = 1tCK, WR = 12 NOTE 2. Din n = data-in to column n. NOTE 3.
AS4C512M8D4 CK# T0 T1 T2 T3 T7 T8 T9 T10 T11 T12 T13 WRITE DES DES DES DES DES DES DES DES DES DES T14 T15 T16 T17 T18 DES DES DES DES DES CK tWR CMD WL = AL + CWL = 9 Bank Group ADDR BG a ADDR Bank Col n tWTR 2 Clocks BC4(Fixed) Operation: DQS, DQS# DQ DBI# Din n Din n+1 Din n+2 Din n+3 Din n Din n+1 Din n+2 Din n+3 TRANSITIONING DATA DON'T CARE NOTE 1. BC = 4, AL = 0, CWL = 9, Preamble = 1tCK NOTE 2. Din n = data-in to column n. NOTE 3.
AS4C512M8D4 T0 CK# T1 T5 T8 T9 T10 T11 T13 T12 T15 T14 T16 T18 T17 T19 CK T20 tWR CMD WRITE DES WRITE DES DES DES DES DES DES DES DES DES DES DES Bank Group ADDR BG a BG a or BG b ADDR Bank Col n Bank Col b DES DES tWTR 4 Clocks tCCD_S/L = 5 tWPST tWPRE DQS, DQS# WL = AL + CWL = 9 BL = 8 Din n DQ Din n+1 Din n+2 Din n+3 Din n+4 Din n+5 Din n+6 Din n+7 CRC Din b Din b+1 Din b+2 Din b+3 CRC Din b Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b
AS4C512M8D4 T0 CK# T1 T6 T7 T8 T9 T10 T12 T11 T13 T15 T16 T17 T18 T19 DES DES DES CK T20 tWR WRITE CMD DES WRITE DES READ DES DES DES DES DES DES DES Bank Group ADDR BG a BG a or BG b ADDR Bank Col n Bank Col b DES tWTR 4 Clocks tCCD_S/L = 6 tWPST tRPRE DQS, DQS# WL = AL + CWL = 9 BL = 8 DQ Din n Din n+1 Din n+2 Din n+3 Din n Din n+1 Din n+2 Din n+3 Din n+4 Din n+5 Din n+6 Din n+7 CRC Din b Din b+1 Din b+2 Din b+3 CRC Din b Din b+1 Di
AS4C512M8D4 T0 CK# T1 T2 T6 T7 T8 T9 T11 T10 T13 T12 T14 T15 CK T16 T17 T18 DES DES tWR_CRC_DM WRITE CMD DES DES DES DES DES DES DES DES DES DES DES Bank Group ADDR BG a ADDR Bank Col n DES DES tWTR_S_CRC_DM/tWTR_L_CRC_DM 4 Clocks tWPST tWPRE DQS, DQS# BL = 8 DQ WL = AL + CWL = 9 Din n Din n+1 Din n+2 Din n+3 Din n+4 Din n+5 Din n+6 Din n+7 DM n DM n+1 DM n+2 DM n+3 DM n+4 DM n+5 DM n+6 DM n+7 Din n Din n+1 Din n+2 Din n+3 DM n DM n+1 D
AS4C512M8D4 Read and Write Command Interval Table 44. Minimum Read and Write Command Timings Bank Group Same Different Access type Minimum Read to Write Timing Parameter Note CL - CWL + RBL / 2 + 1 tCK + tWPRE 1,2 Minimum Read after Write Minimum Read to Write CWL + WBL / 2 + tWTR_L 1,3 CL - CWL + RBL / 2 + 1 tCK + tWPRE 1,2 CWL + WBL / 2 + tWTR_S 1,3 Minimum Read after Write Note 1. These timings require extended calibrations times tZQinit and tZQCS. Note 2.
AS4C512M8D4 CRC Polynomial and logic equation The CRC polynomial used by DDR4 is the ATM-8 HEC, X^8+X^2+X^1+1. A combinatorial logic block implementation of this 8-bit CRC for 72-bits of data contains 272 two-input XOR gates contained in eight 6 XOR gate deep trees. The CRC polynomial and combinatorial logic used by DDR4 is the same as used on GDDR5. The error coverage from the DDR4 polynomial used is shown in the following table. Table 45.
AS4C512M8D4 Write CRC for x4, x8 and x16 devices The Controller generates the CRC checksum and forms the write data frames as below tables. For a x8 DRAM the controller must send 1’s in the transfer 9 if CRC is enabled and must send 1’s in transfer 8 and transfer 9 of the DBI# lane if DBI function is enabled. For a x16 DRAM the controller must send 1’s in the transfer 9 if CRC is enabled and must send 1’s in transfer 8 and transfer 9 of the LDBI# and UDBI# lanes if DBI function is enabled.
AS4C512M8D4 CRC Error Handling CRC Error mechanism shares the same ALERT# signal for reporting errors on writes to DRAM. The controller has no way to distinguish between CRC errors and Command/Address/Parity errors other than to read the DRAM mode registers. This is a very time consuming process in a multi-rank configuration. To speed up recovery for CRC errors, CRC errors are only sent back as a pulse. The minimum pulse-width is six clocks.
AS4C512M8D4 CRC Frame Format with BC4 DDR4 SDRAM supports CRC function for Write operation for Burst Chop 4 (BC4). The CRC function is programmable using DRAM mode register and can be enabled for writes. When CRC is enabled the data frame length is fixed at 10UI for both BL8 and BC4 operations. DDR4 SDRAM also supports burst length on the fly with CRC enabled. This is enabled using mode register.
AS4C512M8D4 There are two identical CRC trees for x16 devices, each have CRC tree inputs of 36 bits. When A2 = 0, input bits D[67:64] are used if DBI# or DM# functions are enabled; if DBI# and DM# are disabled, then D[67:64] are 1s. The input bits D[139:136] are used if DBI# or DM# functions are enabled; if DBI# and DM# are disabled, then D[139:136] are 1s. When A2 = 1, data bits D[7:4] are used as inputs for D[3:0], D[15:12] are used as inputs for D[11:8], and so forth, for the CRC tree.
AS4C512M8D4 Example shown below of CRC tree when X8 is used in BC4 mode, x4 and x16 have similar differences.
AS4C512M8D4 Post Package Repair (hPPR) DDR4 supports Fail Row address repair as optional feature for 4Gb. Supporting hPPR is identified via datasheet and SPD in Module so should refer to DRAM manufacturer’s Datasheet. PPR provides simple and easy repair method in the system and Fail Row address can be repaired by the electrical programming of Electrical-fuse scheme. With hPPR, DDR4 can correct 1Row per Bank Group Electrical-fuse cannot be switched back to un-fused states once it is programmed.
AS4C512M8D4 Hard Fail Row Address Repair (WRA Case) The following is procedure of hPPR with WRA command. 1. Before entering ‘hPPR’ mode, All banks must be Precharged; DBI and CRC Modes must be disabled. 2. Enable hPPR using MR4 bit “A13=1” and wait tMOD. 3. Issue guard Key as four consecutive MR0 commands each with a unique address field A[17:0]. Each MR0 command should space by tMOD. 4. Issue ACT command with Fail Row address. 5. After tRCD, Issue WRA with Valid address.
AS4C512M8D4 T0 T1 Ta0 Tb0 Tc0 Tc1 CMD MRS4 MRS0 ACT WRA DES BG VALID VALID BGf BGf BA VALID VALID BAf VALID VALID CK# CK VALID ADDR (A13=1) Td0 Td1 Te0 Te1 Te2 DES DES DES DES REF/ DES REF/ DES NA NA NA NA NA NA BAf NA NA NA NA NA VALID NA NA NA NA NA Tf1 Tg0 Tg1 Th0 PRE REF/ DES MRS4 DES VALID REF/ DES NA VALID NA VALID NA VALID REF/ DES NA NA VALID NA VALID NA VALID REF/ DES NA NA VALID NA NA VALID REF/ DES Tf0
AS4C512M8D4 Soft Post Package Repair (sPPR) Soft Post Package Repair (sPPR) is a way to quickly, but temporarily, Repair a row element in a Bank Group on a DDR4 DRAM device, contrasted to hard Post Package Repair which takes longer but is permanent repair of a row element. There are some limitations and differences between sPPR and hPPR. Table 55.
AS4C512M8D4 Soft Repair of a Fail Row Address The following is the procedure of sPPR with WR command. Note that during the soft repair sequence, no refresh is allowed. 1. Before entering ‘sPPR’ mode, all banks must be Precharged; DBI and CRC Modes must be disabled. 2. Enable sPPR using MR4 bit “A5=1” and wait tMOD. 3. Issue Guard Key as four consecutive MR0 commands each with a unique address field A[17:0]. Each MR0 command should space by tMOD. MR0 Guard Key sequence is same as hPPR. 4.
AS4C512M8D4 On-Die Termination ODT (On-Die Termination) is a feature of the DDR4 SDRAM that allows the DRAM to change termination resistance for each DQ,DQS, DQS# and DM# for x8 configuration (and TDQS, TDQS# for x8 configuration, when enabled via A11=1 in MR1) via the ODT control pin or Write Command or Default Parking value with MR setting.
AS4C512M8D4 ODT Mode Register and ODT State Table The ODT Mode of DDR4 device has 4 states, Data Termination Disable, RTT_WR, RTT_NOM and RTT_PARK. And the ODT Mode is enabled if any of MR1 A[10:8] or MR2 A[10:9] or MR5 A[8:6] are non zero. When enabled, the value of RTT is determined by the settings of these bits. After entering Self-Refresh mode, DRAM automatically disables ODT termination and set Hi-Z as termination state regardless of these setting.
AS4C512M8D4 On-die termination effective resistances are defined and can be selected by any or all of the following options: MR1 A[10:8] (RTT_NOM) - Disable, 240Ω, 120Ω, 80Ω, 60Ω, 48Ω, 40Ω, and 34Ω. MR2 A[11:9] (RTT_WR) - Disable, 240Ω,120Ω, and 80Ω. MR5 A[8:6] (RTT_PARK) - Disable, 240Ω, 120Ω, 80Ω, 60Ω, 48Ω, 40Ω, and 34Ω. ODT is applied to the following inputs: X8: DQs, DM#, DQS, DQS#, TDQS, and TDQS# inputs.
AS4C512M8D4 Table 58. ODT Electrical Characteristics RZQ=240Ω ±1% entire temperature operation range; after proper ZQ calibration RTT Vout Min. Nom. Max. Unit Note VOLdc= 0.5 x VDDQ 0.9 1 1.25 RZQ 1,2,3 240Ω VOMdc= 0.8 x VDDQ 0.9 1 1.1 RZQ 1,2,3 VOHdc= 1.1 x VDDQ 0.8 1 1.1 RZQ 1,2,3 VOLdc= 0.5 x VDDQ 0.9 1 1.25 RZQ/2 1,2,3 120Ω VOMdc= 0.8 x VDDQ 0.9 1 1.1 RZQ/2 1,2,3 VOHdc= 1.1 x VDDQ 0.8 1 1.1 RZQ/2 1,2,3 VOLdc= 0.5 x VDDQ 0.9 1 1.25 RZQ/3 1,2,3 80Ω VOMdc= 0.8 x VDDQ 0.9 1 1.1 RZQ/3 1,2,3 VOHdc= 1.
AS4C512M8D4 Synchronous ODT Mode Synchronous ODT mode is selected whenever the DLL is turned on and locked.
AS4C512M8D4 Timing Parameter In synchronous ODT mode, the following parameters apply: DODTLon, DODTLoff, RODTLoff, RODTLon4, RODTLon8, tADC (MIN) (MAX). tADC (MIN) and tADC (MAX) are minimum and maximum RTT change timing skew between different termination values. These timing parameters apply to both the synchronous ODT mode and the data termination disable mode. When ODT is asserted, it must remain high until minimum ODTH4 (BL = 4) or ODTH8 (BL = 8) is satisfied.
AS4C512M8D4 ODT During Reads Because the DDR4 DRAM cannot terminate with RTT and drive with RON at the same time; RTT may nominally not be enabled until the end of the postamble as shown in the example below. At cycle T25, the device turns on the termination when it stops driving, which is determined by t HZ. If the DRAM stops driving early (that is, tHZ is early), then tADC (MIN) timing may apply. If the DRAM stops driving late (that is, tHZ is late), then the DRAM complies with tADC (MAX) timing.
AS4C512M8D4 Dynamic ODT In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the device can be changed without issuing an MRS command. This requirement is supported by the dynamic ODT feature, described below. Functional Description The dynamic ODT mode is enabled if bit A9 or A10 of MR2 is set to 1. Three RTT values are available: RTT_NOM, RTT_WR, and RTT_PARK.
AS4C512M8D4 ODT Timing Diagrams The following pages provide example timing diagrams diff CK# CK CMD T0 T1 T2 T8 T9 T10 T11 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 WR DODTLon = WL - 2 ODT DODTLoff = WL - 2 ODTLcnw tADC(max) tADC(min) RTT tADC(max) tADC(min) RTT_PARK tADC(max) tADC(min) RTT_WR tADC(max) tADC(min) RTT_PARK RTT_NOM RTT_PARK ODTLcwn TRANSITIONING DATA Figure 168.
AS4C512M8D4 Asynchronous ODT Mode Asynchronous ODT mode is selected when DLL is disabled by MR1 bit A0=’0’b. In asynchronous ODT timing mode, internal ODT command is not delayed by either the Additive latency (AL) or relative to the external ODT signal (RTT_NOM). In asynchronous ODT mode, the following timing parameters apply tAONAS,min, max, tAOFAS,min,max.
AS4C512M8D4 ODT buffer disabled mode for Power down DRAM does not provide RTT_NOM termination during power down when ODT input buffer deactivation mode is enabled in MR5 bit A5. To account for DRAM internal delay on CKE line to disable the ODT buffer and block the sampled output, the host controller must continuously drive ODT to either low or high when entering power down (from tDODToff+1 prior to CKE low till tCPDED after CKE low). The ODT signal may be floating after tCPDEDmin has expired.
AS4C512M8D4 ODT Timing Definitions Test Load for ODT Timings Different than for timing measurements, the reference load for ODT timings is defined below VDDQ CK, CK# DQ, DM# DQS, DQS# DUT Rterm=50ohm VTT = VSSQ VSSQ Timing Reference Point Figure 173. ODT Timing Reference Load ODT Timing Definitions Definitions for tADC, tAONAS and tAOFAS are provided in the table and measurement reference settings are provided in the subsequent.
AS4C512M8D4 DODTLoff DODTLon Begin point:Rising edge of CK,CK# defined by the end point of DODTLoff. Begin point:Rising edge of CK,CK# defined by the end point of DODTLon. tADC tADC End point:Extrapolated point at VRTT_NOM VRTT_NOM VRTT_NOM VSW2 DQ,DM DQS, DQS# VSW1 VSSQ VSSQ End point:Extrapolated point at VSSQ Figure 174. Definition of tADC at Direct ODT Control Begin point:Rising edge of CK,CK# defined by the end point of ODTLcwn4 or ODTLcwn8.
AS4C512M8D4 Rising edge of CK,CK# with ODT being first registered low. Rising edge of CK,CK# With ODT being first registered high. tAONAS tAOFAS VRTT_NOM End point:Extrapolated point at VRTT_NOM VRTT_NOM VSW2 DQ,DM DQS, DQS# VSW1 VSSQ VSSQ End point:Extrapolated point at VSSQ Figure 176. Definition of tAOFAS and tAONAS Confidential - 156 of 196 - Rev.1.0. Aug.
AS4C512M8D4 Table 64. Absolute Maximum DC Ratings Symbol Values Unit Note VDD Voltage on VDD pin relative to VSS -0.3 ~ 1.5 V 1,3 VDDQ Voltage on VDDQ pin relative to VSS -0.3 ~ 1.5 V 1,3 VPP Voltage on VPP pin relative to VSS -0.3 ~ 3.0 V 4 Voltage on any pin except VREFCA relative to VSS -0.3 ~ 1.5 V 1,3,5 VIN, VOUT Parameter TSTG -55 ~ 100 1,2 Storage Temperature °C Note 1.
AS4C512M8D4 AC and DC Input Measurement Levels Table 67. Single-Ended AC and DC Input Levels for Command and Address Symbol VIH.CA(DC75) VIL.CA(DC75) VIH.CA(AC100) VIL.CA(AC100) VREFCA(DC) DDR4-2400 Parameter DDR4-2666 Min. Max. Min. Max. VREFCA + 0.075 VDD TBD TBD VSS VREFCA 0.075 TBD TBD AC input logic high VREF + 0.1 VDD TBD TBD AC input logic low - VREF 0.1 TBD TBD 0.49 x VDD 0.
AS4C512M8D4 Address, Command and Control Overshoot and Undershoot specifications Table 70. AC overshoot/undershoot for Address, Command and Control pins Symbol Parameter DDR4-2400 DDR4-2666 Unit VAOSP Maximum peak amplitude above VAOS 0.06 TBD V VAOS Upper boundary of overshoot area AAOS1 VAUS Maximum peak amplitude allowed for undershoot VDD + 0.24 TBD V 0.30 TBD V AAOS2 AAOS1 Maximum overshoot area per 1 tCK above VAOS 0.
AS4C512M8D4 Table 73. Capacitance Symbol DDR4-2400/2666 Parameter Min. Max. Unit Note CIO Input/output capacitance 0.55 1.15 pF 1,2,3 CDIO Input/output capacitance delta -0.1 0.1 pF 1,2,3,11 - 0.05 pF 1,2,3,5 0.2 0.7 pF 1,3 - 0.05 pF 1,3,4 Input capacitance(CTRL, ADD, CMD pins only) 0.2 0.7 pF 1,3,6 Input capacitance delta (All CTRL pins only) -0.1 0.1 pF 1,3,7,8 Input capacitance delta (All ADD/CMD pins only) -0.1 0.
AS4C512M8D4 Table 74. DRAM package electrical specifications Symbol Parameter DDR4-2400/2666 Min. Max. 85 Unit Note Ω 1,2,4,5,10 ZIO IInput/output Zpkg 45 TdIO Input/output Pkg Delay 14 42 ps 1,3,4,5,10 Lio Input/Output Lpkg - 3.3 nH 10,11 Cio Input/Output Cpkg - 0.78 pF 10,12 ZIO DQS DQS, DQS# Zpkg 45 85 Ω 1,2,5,10 TdIO DQS DQS, DQS# Pkg Delay 14 42 ps 1,3,5,10 10,11 Lio DQS DQS Lpkg - 3.3 nH Cio DQS DQS Cpkg - 0.
AS4C512M8D4 IDD and IDDQ Specification Parameters and Test conditions In this chapter, IDD, IPP and IDDQ measurement conditions such as test load and patterns are defined and setup and test load for IDD, IPP and IDDQ measurements are also described here.
AS4C512M8D4 RESET# CK/CK# IDD IPP IDDQ VDD VPP VDDQ DDR4 SDRAM CKE CS# ACT#, RAS#, CAS#, WE A, BG,BA ODT ZQ VSS DQS/DQS# DQ DM VSSQ NOTE 1. DIMM level Output test load condition may be different from above. Figure 177. Measurement Setup and Test Load for IDD, IPP and IDDQ Measurements IDDQ TestLad Application specific memory channel environment Channel IO Power Simulation Channel IO Power Simulation Channel IO Power Simulation X X Channel IO Power Number Figure 178.
AS4C512M8D4 Table 75. Timings used for IDD, IPP and IDDQ Measurement Symbol tCK CL CWL nRCD nRC nRAS nRP nFAW nRRDS nRRDL tCCD_S tCCD_L tWTR_S tWTR_L nRFC 4Gb Confidential x4 x8 x16 x4 x8 x16 x4 x8 x16 DDR4-2400 0.833 17 16 17 57 39 17 16 26 36 4 4 7 4 4 7 4 6 3 9 313 DDR4-2666 0.75 19 18 19 62 43 19 16 28 40 4 4 7 4 4 7 4 7 4 10 347 - 164 of 196 - Unit ns nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK Rev.1.0. Aug.
AS4C512M8D4 Table 76.
AS4C512M8D4 IDD3P IPP3P IDD4R IDD4RA IDD4RB IPP4R IDDQ4R (Optional) IDDQ4RB (Optional) IDD4W IDD4WA IDD4WB IDD4WC IDD4W_p ar IPP4W IDD5B IPP5B IDD5F2 IPP5F2 IDD5F4 IPP5F4 IDD6N IPP6N Confidential Active Power-Down Current CKE: Low; External clock: On; tCK, CL: see IDD timing Table; BL: 81; AL: 0; CS#: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM#: stable at 1; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Regis
AS4C512M8D4 Self-Refresh Current: Extended Temperature Range TCASE: 0 - 95°C; Low Power Auto Self Refresh (LP ASR): Extended4; CKE: Low; External clock: Off; CK and CK#: IDD6E LOW; CL: see IDD timing table; BL: 81; AL: 0; CS#, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM#:stable at 1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL Self Refresh IPP Current: Extended Temperature Range IPP6E Sam
AS4C512M8D4 Table 77. IDD0, IDD0A and IPP0 Measurement - Loop Pattern[1] Static High Toggling CK/ SubCKE CK# Loop Cycle Number CMD CS# ACT# RAS#/ CAS#/ WE#/ A16 A15 A14 [2] BA0-1 A12 /BC# A13, A11 A10 0 0 ACT 0 0 0 0 0 0 0 0 0 0 0 0 0 1-2 D,D 1 0 0 0 0 0 3-4 D#,D# 1 1 1 1 1 0 0 0 0 0 0 0 3[2] 3 0 0 0 0 … 0 nRAS 0 … Repeat pattern 1...
AS4C512M8D4 Table 78. IDD1, IDD1A and IPP1 Measurement - Loop Pattern[1] CK/ SubCKE CK# Loop Cycle Number CMD CS# ACT# 0 0 ACT 0 0 0 0 0 0 0 1-2 D,D 1 0 0 0 0 0 3-4 D#,D# 1 1 1 1 1 0 … Static High Toggling 0 nRCD-AL 0 … 0 nRAS 0 … RAS#/ CAS#/ WE#/ A16 A15 A14 [2] BA0-1 A12/ BC# A13, A11 0 0 0 0 0 0 0 0 0 0 0 0 0 3[2] 3 0 0 0 ODT BG0-1 [3] A10 A9-A7 A6-A3 A2-A0 Data 0 0 - 0 0 0 - 7 F 0 - Repeat pattern 1...
AS4C512M8D4 Table 79.
AS4C512M8D4 Table 80.
AS4C512M8D4 Table 81.
AS4C512M8D4 Table 82.
AS4C512M8D4 Table 83.
AS4C512M8D4 Table 84.
AS4C512M8D4 Table 85. IDD7 Measurement - Loop Pattern[1] CK/ SubCKE CK# Loop Static High Toggling 0 Cycle Number CMD CS# ACT# 0 ACT 0 0 0 1 0 0 RAS#/ CAS#/ WE#/ A16 A15 A14 0 0 0 ODT 0 RDA 0 1 1 0 1 0 2 D 1 0 0 0 0 0 3 D# 1 1 1 1 1 0 ACT 0 0 0 0 … 1 nRRD BG0-1 [2] BA0-1 A12/ BC# A13, A11 A10 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 [2] 3 0 0 0 3 0 0 0 - 7 F 0 - 0 0 Repeat pattern 2...3, until nRRD - 1, if nRRD > 4.
AS4C512M8D4 Table 86. IDD and IDDQ Specification Parameters and Test conditions Parameter Symbol DDR4-2400 DDR4-2666 Max. Max.
AS4C512M8D4 Operating Burst Write Current with Write DBI IDD4WB 155 172 mA Operating Burst Write Current with Write CRC IDD4WC 151 168 mA Operating Burst Write Current with CA Parity IDD4W_par 176 189 mA Operating Burst Write IPP Current IPP4W 3 4 mA Burst Refresh Current (1X REF) IDD5B 170 180 mA Burst Refresh Write IPP Current (1X REF) IPP5B 22 25 mA Burst Refresh Current (2X REF) IDD5F2 179 189 mA Burst Refresh Write IPP Current (2X REF) IPP5F2 23 27 mA Burst
AS4C512M8D4 Table 87. Timing Parameters Symbol tAA DDR4-2400 Parameter Min. Internal read command to first data tAA_DBI Internal read command to first data with read DBI enabled tRCD ACT to internal read or write delay time tRP PRE command period tRAS ACT to PRE command period tRC ACT to ACT or REF command period Speed Bins CWL Normal Read DBI 14.16 tAA(min) + 3 tCK 14.16 DDR4-2666 Max. 18 tAA(max) + tCK - Min. 3 Unit Max. 14.25 tAA(min) + 3 tCK 14.
AS4C512M8D4 tERR(18per) tERR(nper) tIS(base) tIS(VREF) tIH(base) tIH(VREF) tIPW tCCD_L34 tCCD_S34 tRRD_S(1K) 34 tRRD_L(1K)34 tFAW_1K34 tWTR_S 1,2,34 tWTR_L1,34 tRTP34 tWR1 tWR_CRC_DM1,28 tWTR_S_CRC_DM 2,29,34 tWTR_L_CRC_DM 3,30,34 tDLLK tMRD tMOD50 tMPRR 33 tWR_MPR tDAL(min) tPDA_S45,47 tPDA_H46,47 tCAL tMRD_tCAL tMOD_tCAL tDQSQ13,18,39,49 tQH13,17,18,39,49 tDVWd17,18,39,49 tDVWp17,18,39,49 39 tLZ(DQ) tHZ(DQ)39 tRPRE39,40, 44 tRPRE239,41,44 tRPST39,45 tQSH21,39 Confidential Cumulative error
AS4C512M8D4 tQSL 20,39 tWPRE42 tWPRE243 tWPST tLZ(DQS)39 tHZ(DQS)39 tDQSL tDQSH tDQSS42 tDQSS2 43 tDSS tDSH tDQSCK(DLL On) 37,38,39 tDQSCKI(DLL On) 37,38,39 DQS, DQS# differential output low time DQS, DQS# differential Write Preamble (1 clock preamble) DQS, DQS# differential Write Preamble (2 clock preamble) DQS, DQS# differential Write Postamble DQS, DQS# low impedance time (Referenced from RL-1) DQS, DQS# high impedance time (Referenced from RL+BL/2) DQS, DQS# differential input low pulse width
AS4C512M8D4 tMRD_PDA Mode Register Set command cycle time in PDA mode tMOD_PDA tAONAS tAOFAS tADC tWLMRD12 tWLDQSEN 12 tWLS tWLH tWLO tWLOE tPAR_UNKNOWN tPAR_ALERT_ON tPAR_ALERT_PW tPAR_ALERT_RSP PL tCRC_ALERT tCRC_ALERT_PW tXPR_GEAR tXS_GEAR tSYNC_GEAR27 tCMD_GEAR27 tGEAR_setup tGEAR_hold max(16nCK , 10ns) tMOD Mode Register Set command update delay in PDA mode ODT Timing Asynchronous RTT turn-on delay (Power-Down with DLL frozen) Asynchronous RTT turn-off delay (Power-Down with DLL frozen) RTT
AS4C512M8D4 Note 19. DRAM DBI mode is enabled. Note 20. tQSL describes the instantaneous differential output low pulse width on DQS - DQS#, as measured from on falling edge to the next consecutive rising edge. Note 21. tQSH describes the instantaneous differential output high pulse width on DQS – DQS#, as measured from on falling edge to the next consecutive rising edge. Note 22. There is no maximum cycle time limit besides the need to satisfy the refresh interval t REFI. Note 23.
AS4C512M8D4 AC and DC output Measurement levels Output Driver DC Electrical Characteristics The DDR4 driver supports two different RON values. These RON values are referred as strong(low RON) and weak mode(high RON). A functional representation of the output buffer is shown in the figure below.
AS4C512M8D4 Table 88. Output Driver DC Electrical Characteristics, assuming RZQ = 240ohm; RON_NOM entire operating temperature range; after proper ZQ calibration Resistor Vout VOLdc= 0.5 x VDDQ VOMdc= 0.8 x VDDQ VOHdc= 1.1 x VDDQ VOLdc= 0.5 x VDDQ VOMdc= 0.8 x VDDQ VOHdc= 1.1 x VDDQ VOLdc= 0.5 x VDDQ VOMdc= 0.8 x VDDQ VOHdc= 1.1 x VDDQ VOLdc= 0.5 x VDDQ VOMdc= 0.8 x VDDQ VOHdc= 1.1 x VDDQ RON34Pd 34Ω RON34Pu RON48Pd 48Ω RON48Pu Min. 0.8 0.9 0.9 0.9 0.9 0.8 0.8 0.9 0.9 0.9 0.9 0.8 Nom.
AS4C512M8D4 ALERT# output Drive Characteristic A functional representation of the output buffer is shown in the figure below. Output driver impedance RON is defined as follows: RONPd = Vout | I out | under the condition that RONPu is off Alert Driver Alert DRAM Iout RONPd Vout IPd VSSQ Figure 180. ALERT# output Drive Characteristic Table 89. ALERT Driver Voltage Resistor Vout Min. VOLdc= 0.1 x VDDQ 0.3 RONPd VOMdc= 0.8 x VDDQ 0.4 VOHdc= 1.1 x VDDQ 0.4 Note 1. VDDQ voltage is at VDDQ DC.
AS4C512M8D4 Single-ended AC & DC Output Levels Table 90. Single-ended AC & DC output levels Symbol Vout DDR4-2400/2666 Unit Note VOH(DC) DC output high measurement level (for IV curve linearity) 1.1 x VDDQ V VOM(DC) DC output mid measurement level (for IV curve linearity 0.8 x VDDQ V VOL(DC) DC output low measurement level (for IV curve linearity) 0.5 x VDDQ V VOH(AC) AC output high measurement level (for output SR) (0.7 + 0.15) x VDDQ V 1 VOL(AC) AC output low measurement level (for output SR) (0.
AS4C512M8D4 Single-ended Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals. Table 92. Single-ended output slew rate definition Measured Defined by From To Single ended output slew rate for rising edge VOL(AC) VOH(AC) [VOH(AC)-VOL(AC)] / Delta TRse Single ended output slew rate for falling edge VOH(AC) VOL(AC) [VOH(AC)-VOL(AC)] / Delta TFse Note 1.
AS4C512M8D4 Slew Rate Definitions for Differential Input Signals (CK) Table 96. Differential Input Slew Rate Definition Measured From To Differential input slew rate for rising edge (CK - CK#) VILdiffmax VIHdiffmin Differential input slew rate for falling edge (CK - CK#) VIHdiffmin VILdiffmax Note 1. The differential signal (i,e., CK - CK#) must be linear between these thresholds. Description Defined by IHdiffmin IHdiffmin – VILdiffmax – VILdiffmax Differential Input Cross Point Voltage Table 97.
AS4C512M8D4 Differential swing requirements for DQS (DQS – DQS#) Table 99. Differential AC and DC Input Levels for DQS Symbol DDR4-2400 Min. Max. 160 -160 Parameter DDR4-2666 Min. Max. TBD TBD TBD TBD Unit Note VIHDiffPeak VIH.DIFF.Peak Voltage mV 1,2 VILDiffPeak VIL.DIFF.Peak Voltage mV 1,2 Note 1. Used to define a differential signal slew-rate. Note 2.
AS4C512M8D4 Differential Input Cross Point Voltage Table 101. Differential Input Slew Rate Definition for DQS, DQS# Measured Description Defined by From To Differential input slew rate for rising edge (DQS - DQS#) VILDiff_DQS VIHDiff_DQS |VILDiff_DQS - VIHDiff_DQS| / DeltaTRdiff Differential input slew rate for falling edge (DQS - DQS#) VIHDiff_DQS VILDiff_DQS |VILDiff_DQS - VIHDiff_DQS| / DeltaTFdiff Table 102.
AS4C512M8D4 Electrical Characteristics and AC Timing Reference Load for AC Timing and Output Slew Rate Reference Load for AC Timing and Output Slew Rate represents the effective reference load of 50 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements. RON nominal of DQ, DQS and DQS# drivers uses 34 ohms to specify the relevant AC timing paraeter values of the device. The maximum DC High level of Output signal = 1.
AS4C512M8D4 Clock Specification The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result in malfunction of the device. Definitions for tCK(abs): tCK(abs) is defined as the absolute clock period, as measured from one rising edge to the next consecutive rising edge. tCK(abs) is not subject to production test.
AS4C512M8D4 Command, Control, and Address Setup, Hold, and Derating The total tIS (setup time) and tIH (hold time) required is calculated to account for slew rate variation by adding the data sheet tIS(base) values, the VIL(AC)/VIH(AC) points, and tIH(base) values, the VIL(DC)/VIH(DC) points; to the ΔtIS and ΔtIH derating values, respectively. The base values are derived with single-end signals at 1V/ns and differential clock at 2V/ns. Example: tIS (total setup time) = tIS(base) + ΔtIS.
AS4C512M8D4 Package Outline Drawing Information Symbol A A1 A2 D E D1 E1 F e b D2 Dimension in inch Min Nom Max --0.047 0.010 -0.016 --0.008 0.291 0.295 0.299 0.413 0.417 0.421 -0.252 --0.378 --0.126 --0.031 -0.016 0.018 0.020 --0.081 Dimension in mm Min Nom Max --1.20 0.25 -0.40 --0.20 7.40 7.50 7.60 10.50 10.60 10.70 -6.40 --9.60 --3.20 --0.80 -0.40 0.45 0.50 --2.05 Figure 182. 78-Ball FBGA Package 7.5x10.6x1.2mm(max) Confidential - 195 of 196 - Rev.1.0. Aug.
AS4C512M8D4 PART NUMBERING SYSTEM AS4C DRAM 512M8D4 512M8=512Mx8 D4=DDR4 -83/75 B 83=1200MHz 75=1333MHz B=FBGA C/I C=Commercial (Extended) 0°C~ 95°C I=Industrial -40°C~ 95°C N XX Indicates Pb and Halogen Free Packing Type None:Tray TR:Reel Alliance Memory, Inc. 511 Taylor Way, San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved © Copyright 2007 Alliance Memory, Inc. All rights reserved.
