Datasheet

Ta1 Ta2 Tb0 Tb1 Tb2Ta0
t
MOD_PAR
MRSDES DES DES VALID DES
PL = 0
CK#
CK
CMD
Settings
Updating Setting PL = N
NOTE 1. tMOD_PAR = tMOD + N; where N is the programmed parity latency with the MRS command
entering CA parity mode.
NOTE 2. Parity check is not available at Ta1 of MRS command due to PL=0 being valid.
NOTE 3. In case parity error happens at Tb1 of VALID command, tPAR_ALERT_ON is ‘N[nCK] + 6[ns]’.
Enable Parity change
PL from 0 to N
Figure 65. Parity entry timing example - tMOD_PAR
Ta1 Ta2 Tb0 Tb1 Tb2Ta0
t
MRD_PAR
MRSDES DES DES MRS DES
PL = N
CK#
CK
CMD
Settings
Updating Setting PL = 0
NOTE 1. tMRD_PAR = tMOD + N; where N is the programmed parity latency prior to the MRS command
exiting CA parity mode.
NOTE 2. In case parity error happens at Ta1 of MRS command, tPAR_ALERT_ON is ‘N[nCK] + 6[ns]’.
NOTE 3. Parity check is not available at Tb1 of MRS command due to disabling parity mode.
Disable Parity change
PL from N to 0
Figure 66. Parity exit timing example - tMRD_PAR
Ta1 Ta2 Tb0 Tb1 Tb2Ta0
t
MOD_PAR
MRSDES DES DES VALID DES
PL = N
CK#
CK
CMD
Settings
Updating Setting PL = 0
NOTE 1. tMOD_PAR = tMOD + N; where N is the programmed parity latency prior to the MRS command
exiting CA parity mode.
NOTE 2. In case parity error happens at Ta1 of MRS command, tPAR_ALERT_ON is ‘N[nCK] + 6[ns]’.
NOTE 3. Parity check is not available at Tb1 of VALID command due to disabling parity mode.
Disable Parity change
PL from N to 0
Figure 67. Parity exit timing example - tMOD_PAR
AS4C512M8D4
Confidential
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Rev.1.0. Aug.2019