Datasheet

Data Mask (DM), Data Bus Inversion (DBI) and TDQS
DDR4 SDRAM supports Data Mask (DM) function and Data Bus Inversion (DBI) function in x8 configuration.
x8 DDR4 SDRAM supports TDQS function.
DM, DBI & TDQS functions are supported with dedicated one pin labeled as DM#/DBI#/TDQS. The pin is bi-
directional pin for DRAM. The DM#/DBI# pin is Active Low as DDR4 supports V
DDQ
reference termination.
TDQS function does not drive actual level on the pin.
DM, DBI & TDQS functions are programmable through DRAM Mode Register (MR). The MR bit location is
bit A11 in MR1 and bit A12:A10 in MR5.
Write operation: Either DM or DBI function can be enabled but both functions cannot be enabled simultanteously.
When both DM and DBI functions are disabled, DRAM turns off its input receiver and does not expect any
valid logic level.
Read operation: Only DBI function applies. When DBI function is disabled, DRAM turns off its output driver
and does not drive any valid logic level.
TDQS function: When TDQS function is enabled, DM & DBI functions are not supported. When TDQS function
is disabled, DM and DBI functions are supported as described below. When enabled, the same
termination resistance function is applied to the TDQS/TDQS# pins that is applied to DQS/DQS# pins.
Table 24. TDQS Function Matr
TDQS (MR1 bit A11)
DM (MR5 bit A10)
Write DBI (MR5 bit A11)
Read DBI (MR5 bit A12)
0 (TDQS Disabled)
Enabled
Disabled
Enabled or Disabled
Disabled
Enabled
Enabled or Disabled
Disabled
Disabled
Enabled or Disabled
1 (TDQS Enabled)
Disabled
Disabled
Disabled
DM function during Write operation: DRAM masks the write data received on the DQ inputs if DM# was
sampled Low on a given byte lane. If DM# was sampled High on a given byte lane, DRAM does not mask the
write data and writes into the DRAM core.
DBI function during Write operation: DRAM inverts write data received on the DQ inputs if DBI# was
sampled Low on a given byte lane. If DBI# was sampled High on a given byte lane, DRAM leaves the data
received on the DQ inputs non-inverted.
DBI function during Read operation: DRAM inverts read data on its DQ outputs and drives DBI# pin Low
when the number of ‘0’ data bits within a given byte lane is greater than 4; otherwise DRAM does not invert
the read data and drives DBI# pin High.
Table 25. DQ Frame Format
Write
Data transfer
0
1
2
3
4
5
6
7
DQ[7:0]
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
DM# or DBI#
DM0 or
DBI0
DM1 or
DBI1
DM2 or
DBI2
DM3 or
DBI3
DM4 or
DBI4
DM5 or
DBI5
DM6 or
DBI6
DM7 or
DBI7
Read
Data transfer
0
1
2
3
4
5
6
7
DQ[7:0]
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
DBI#
DBI0
DBI1
DBI2
DBI3
DBI4
DBI5
DBI6
DBI7
AS4C512M8D4
Confidential
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Rev.1.0. Aug.2019