Datasheet

CRC Error Handling
CRC Error mechanism shares the same ALERT# signal for reporting errors on writes to DRAM. The controller
has no way to distinguish between CRC errors and Command/Address/Parity errors other than to read the
DRAM mode registers. This is a very time consuming process in a multi-rank configuration.
To speed up recovery for CRC errors, CRC errors are only sent back as a pulse. The minimum pulse-width is
six clocks. The latency to ALERT# signal is defined as t
CRC_ALERT
in the figure below.
DRAM will set CRC Error Clear bit in A3 of MR5 to '1' and CRC Error Status bit in MPR3 of page1 to '1' upon
detecting a CRC error. The CRC Error Clear bit remains set at '1' until the host clears it explicitly using an
MRS command.
The controller upon seeing an error as a pulse width will retry the write transactions. The controller understands
the worst case delay for ALERT# (during init) and can back up the transactions accordingly or the controller
can be made more intelligent and try to correlate the write CRC error to a specific rank or a transaction. The
controller is also responsible for opening any pages and ensuring that retrying of writes is done in a coherent
fashion.
The pulse width may be seen longer than six clocks at the controller if there are multiple CRC errors as the
ALERT# is a daisy chain bus.
T1 T2 T3 T4 T5 T6 Ta0 Ta1 Ta2T0 Ta3
Don't Care
D0 D1 D2 D3 D4 D5 D6 D7
CK#
CK
DQ
Alert#
Ta4 Ta5
CRC 1'S
t
CRC_ALERT
CRC ALERT_PW(min)
CRC ALERT_PW(max)
NOTE 1. CRC ALERT_PW IS Specified from the point Where the DRAM starts to drive the signal low to the point where the DRAM driver releases and the
controller starts to pull the signal up.
TIME BREAK
Figure 158. CRC Error Reporting
Table 49. CRC Error Timing Parameters
Symbol
Parameter
Min.
Max.
Unit
tCRC_ALERT
CRC error to ALERT# Latency
-
13
ns
CRC ALERT_PW
CRC ALERT_PW
6
10
tCK
!
AS4C512M8D4
Confidential
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Rev.1.0. Aug.2019